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a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 revision: 1.00 date: ??? i? 0?? ?01? ???i? 0?? ?01?
rev. 1.00 ? ???i? 0?? ?01? rev. 1.00 ? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi table of contents eates cpu featu?es ......................................................................................................................... 8 pe?i?he?a? featu?es ................................................................................................................. 8 gene?a? desc?i?tion ......................................................................................... 9 se?ection tab?e ............................................................................................... 10 b?ock diag?am ................................................................................................ 10 pin ?ssignment ............................................................................................... 11 pin desc?i?tion .............................................................................................. 14 ?bso?ute maximum ratings .......................................................................... ?? d.c. cha?acte?istics ....................................................................................... ?4 ?.c. cha?acte?istics ....................................................................................... ?6 lvd & lvr e?ect?ica? cha?acte?istics .......................................................... ?7 ?dc e?ect?ica? cha?acte?istics ..................................................................... ?8 com?a?ato? e?ect?ica? cha?acte?istics ........................................................ ?8 powe? on reset (?c+dc) e?ect?ica? cha?acte?istics .................................. ?8 system ??chitectu?e ...................................................................................... ?9 c?ocking and pi?e?ining ......................................................................................................... ?9 p?og?am counte? ................................................................................................................... ?0 stack ..................................................................................................................................... ?1 ??ithmetic and logic unit C ?lu ........................................................................................... ?1 f?ash p?og?am memo?y ................................................................................. ?? st?uctu?e ................................................................................................................................ ?? s?ecia? vecto?s ..................................................................................................................... ?? look-u? tab?e ........................................................................................................................ ?? tab ?e p?og?am exam??e ........................................................................................................ ?? pa?tia? lock ........................................................................................................................... ?4 in system p?og?amming C isp .............................................................................................. ?5 f?ash memo?y read/w ?ite page size ................................................................................... ?5 isp boot ?oade? ...................................................................................................................... ?7 f?ash p?og?am memo?y registe?s ........................................................................................ ?7 in ????ication p?og?amming C i?p ........................................................................................ 41 enab?e f?ash w ?ite cont?o? p?ocedu?e .................................................................................. 41 f?ash memo?y w ?ite and read p?ocedu?es .......................................................................... 4? in ci?cuit p?og?amming C icp ............................................................................................... 45 on-chi? debug su??o?t C ocds ......................................................................................... 45
rev. 1.00 ? ???i? 0?? ?01? rev. 1.00 ? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ram data memory ......................................................................................... 46 st?uctu?e ................................................................................................................................ 46 special function register description ........................................................ 50 indi?ect ?dd?essing registe?s C i?r0? i?r1 ......................................................................... 50 memo?y pointe?s C mp0? mp1 .............................................................................................. 50 bank pointe? C bp ................................................................................................................. 51 ?ccumu?ato? C ?cc ............................................................................................................... 5? p?og?am counte? low registe? C pcl .................................................................................. 5? look-u? tab? e registe? s C tblp ? tbhp ? tblh ..................................................................... 5? status registe? C st ? tus .................................................................................................... 5? oscillator ........................................................................................................ 54 osci??ato? ove?view ............................................................................................................... 54 system clock confgurations ................................................................................................ 54 exte?na? c?ysta? osci??ato? C hxt .......................................................................................... 55 inte?na? pll f?equency gene?ato? ........................................................................................ 56 inte?na? rc osci??ato? C hirc ............................................................................................... 58 exte?na? ??.768khz c?ysta? osci??ato? C lxt ........................................................................ 58 lxt osci ??ato? low powe? function ...................................................................................... 59 inte?na? ??khz osci??ato? C lirc ........................................................................................... 59 su???ementa?y inte?na? c?ocks ............................................................................................. 60 operating modes and system clocks ......................................................... 60 system c?ocks ...................................................................................................................... 60 system o?e?ation modes ...................................................................................................... 61 cont?o? registe? .................................................................................................................... 6? fast wake-u ? ........................................................................................................................ 64 o?e? ating mode switching and wake-u? .............................................................................. 65 norm? l mode to slow mode switching ........................................................................... 65 slow mode to norm? l mode switching ........................................................................... 67 ente?ing the sleep0 mode .................................................................................................. 67 ente?ing the sleep1 mode .................................................................................................. 67 ente?ing the idle0 mode ...................................................................................................... 68 ente?ing the idle1 mode ...................................................................................................... 68 standby cu??ent conside?ations ........................................................................................... 68 wake-u ? ................................................................................................................................ 69 p?og?amming conside?ations ................................................................................................ 69 watchdog timer ............................................................................................. 70 watchdog time ? c?ock sou?ce .............................................................................................. 70 watchdog time ? cont?o? registe? ......................................................................................... 70 watchdog time ? o?e?ation ................................................................................................... 71 wdt enab ?e/disab? ed using the wdt cont?o? registe? ....................................................... 7?
rev. 1.00 4 ???i? 0?? ?01? rev. 1.00 5 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi reset and initialisation .................................................................................. 73 reset ove?view ..................................................................................................................... 7? reset functions .................................................................................................................... 74 wdtc registe? softwa?e reset .......................................................................................... 77 reset initia? conditions ......................................................................................................... 78 input/output ports ......................................................................................... 88 pu??-high resisto?s ................................................................................................................ 91 po? t wake-u? ........................................................................................................................ 9? po?t ? wake-u ? po?a?ity cont?o? registe? ............................................................................ 94 i/o po?t cont?o? registe?s ..................................................................................................... 95 i/o out?ut cu??ent cont?o? registe?s ................................................................................... 97 i/o out?ut s?ew rate cont?o? registe?s ............................................................................... 98 po?t ? powe? sou?ce cont?o? registe?s ............................................................................. 100 i/o pin st?uctu?es ................................................................................................................ 101 p?og?amming conside?ations .............................................................................................. 10? timer modules C tm .................................................................................... 103 int?oduction ......................................................................................................................... 10? tm o?e?ation ...................................................................................................................... 10? tm c?ock sou?ce ................................................................................................................. 104 tm inte??u?ts ....................................................................................................................... 104 tm exte?na? pins ................................................................................................................. 104 tm in?ut/out?ut pin cont?o? registe?s ............................................................................... 105 p?og?amming conside?ations .............................................................................................. 109 compact type tm C ctm ............................................................................. 110 com? act tm o?e?ation ........................................................................................................ 111 com? act ty? e tm registe? desc?i?tion ............................................................................... 111 com? act ty? e tm o?e? ating modes ................................................................................... 116 com?a?e match out?ut mode .............................................................................................. 116 time ?/counte? mode ............................................................................................................ 119 pwm out?ut mode ............................................................................................................... 119 standard type tm C stm ............................................................................ 122 standa? d tm o?e?ation ....................................................................................................... 1?? standa? d ty? e tm registe? desc?i?tion ............................................................................. 1?? standa? d ty? e tm o?e? ating modes .................................................................................. 1?0 com?a?e out?ut mode ........................................................................................................ 1?0 time ?/counte? mode ........................................................................................................... 1?? pwm out?ut mode .............................................................................................................. 1?? sing?e pu?se mode .............................................................................................................. 1?6 ca?tu?e in?ut mode ............................................................................................................ 1?8
rev. 1.00 4 ???i? 0?? ?01? rev. 1.00 5 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi analog to digital converter ........................................................................ 140 ?/d ove?view ...................................................................................................................... 140 ?/d conve?te? registe? desc?i?tion .................................................................................... 140 ?/d conve?te? data registe?s C ?drl? ?drh ................................................................... 141 ? /d conve?te? cont?o? registe? s C ?dcr0? ?dcr1? ?cer0? ?cer1 ............................... 141 ?/d o?e?ation ..................................................................................................................... 147 ?/d in?ut pins ..................................................................................................................... 148 summa?y of ?/d conve?sion ste?s ..................................................................................... 148 p?og?amming conside?ations .............................................................................................. 149 ?/d t ?ansfe? function ......................................................................................................... 149 ?/d p?og?amming exam??e ................................................................................................. 150 comparators ................................................................................................ 152 com?a?ato? o?e?ation ........................................................................................................ 15? com?a?ato? registe?s ......................................................................................................... 15? com?a?ato? inte??u?t ........................................................................................................... 15? p?og?amming conside?ations .............................................................................................. 15? serial interface module C sim ..................................................................... 155 spi inte?face ....................................................................................................................... 155 spi inte?face o?e?ation ....................................................................................................... 155 spi registe?s ...................................................................................................................... 157 spi communication ............................................................................................................ 160 spi bus enab?e/disab?e ...................................................................................................... 16? spi o?e?ation ...................................................................................................................... 16? e??o? detection .................................................................................................................... 164 i ? c inte?face ........................................................................................................................ 164 i ? c inte?face o?e?ation ........................................................................................................ 165 i ? c registe?s ....................................................................................................................... 165 i ? c bus communication ...................................................................................................... 170 i ? c bus sta?t signa? ............................................................................................................. 171 s?ave ?dd?ess ..................................................................................................................... 171 i ? c bus read/w ?ite signa? .................................................................................................. 171 i ? c bus s?ave ?dd?ess ?cknow?edge signa? ....................................................................... 171 i ? c bus data and ?cknow?edge signa? ............................................................................... 17? i ? c time out function .......................................................................................................... 17? i ? c time out o ?e?ation ........................................................................................................ 174 serial interface C spia ................................................................................ 175 spi? inte?face o?e?ation .................................................................................................... 175 spi? registe?s .................................................................................................................... 176 spi? communication .......................................................................................................... 179 spi? bus enab?e/disab?e .................................................................................................... 181 spi? o?e?ation ................................................................................................................... 18? e??o? detection .................................................................................................................... 18?
rev. 1.00 6 ???i? 0?? ?01? rev. 1.00 7 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi peripheral clock output .............................................................................. 184 pe?i?he?a? c?ock o?e?ation ................................................................................................. 184 interrupts ...................................................................................................... 185 inte??u?t registe?s ............................................................................................................... 185 inte??u?t o?e?ation .............................................................................................................. 19? exte?na? inte??u?t ................................................................................................................. 194 com?a?ato? inte??u?t ........................................................................................................... 194 usb inte??u?t ...................................................................................................................... 194 mu?ti-function inte??u?t ........................................................................................................ 195 ?/d conve?te? inte??u?t ....................................................................................................... 195 time base inte ??u?ts ........................................................................................................... 195 se?ia? inte?face modu?e inte??u?ts C sim inte??u?t .............................................................. 196 se?ia? pe?i?he?a? inte?face inte??u?t C spi? inte??u?t .......................................................... 197 lvd inte ??u?t ....................................................................................................................... 197 tm inte??u?ts ....................................................................................................................... 197 inte??u? t wake-u? function ................................................................................................. 197 p?og?amming conside?ations .............................................................................................. 198 low voltage detector C lvd ....................................................................... 199 lvd registe ? ....................................................................................................................... 199 lvd o ?e?ation ..................................................................................................................... ?00 usb interface ............................................................................................... 200 powe? p?ane ........................................................................................................................ ?00 usb sus? end wake-u? remote wake-u? ........................................................................ ?01 usb inte?face o?e?ation ..................................................................................................... ?0? usb inte?face registe?s ...................................................................................................... ?0? confguration options ................................................................................. 224 application circuits ..................................................................................... 225 instruction set .............................................................................................. 226 int?oduction ......................................................................................................................... ??6 inst? uction timing ................................................................................................................ ??6 moving and t ?ansfe??ing data ............................................................................................. ??6 ??ithmetic o?e?ations .......................................................................................................... ??6 logica? and rotate o?e?ation ............................................................................................. ??7 b?anches and cont?o? t ?ansfe? ........................................................................................... ??7 bit o?e?ations ..................................................................................................................... ??7 tab ?e read o?e?ations ....................................................................................................... ??7 othe? o?e?ations ................................................................................................................. ??7 inst?uction set summa?y ..................................................................................................... ??8
rev. 1.00 6 ???i? 0?? ?01? rev. 1.00 7 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi instruction defnition ................................................................................... 230 package information ................................................................................... 240 ?8-?in ssop(150mi?) out?ine dimensions .......................................................................... ?41 s? w ty ?e 40-?in (6mm6mm fo? 0.75mm) qfn out?ine dimensions ............................... ?4? 48-? in lqfp (7mm7mm) out?ine dimensions .................................................................. ?4? 64-? in lqfp (7mm7mm) out?ine dimensions .................................................................. ?44
rev. 1.00 8 ???i? 0?? ?01? rev. 1.00 9 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi features cpu features ? operating voltage v dd (mcu): f sys =4mhz/6mhz: 2.2v~5.5v f sys =12mhz: 2.7v~5.5v v dd (usb mode): f sys =6mhz/12mhz: 3.3v~5.5v f sys =16mhz: 4.5v~5.5v ? up to 0.25s instruction cycle with 16mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? four oscillators external crystal C hxt external 32.768khz crystal C lxt internal rc C hirc internal 32khz rc C lirc ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? up to 12-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 4k16~16k16 ? ram data memory: 5128~10248 ? usb 2.0 full speed compatible ? up to 8 endpoints supported including endpoint 0 ? all endpoints except endpoint 0 can support interrupt and bulk transfer ? all endpoints except endpoint 0 can be confgured as 8, 16, 32, 64 bytes fifo size ? endpoint 0 support control transfer ? endpoint 0 has 8 byte fifo ? support 3.3v ldo and internal udp 1.5k pull-up resistor ? internal 12mhz rc osc with 0.25% accuracy for all usb modes ? watchdog timer function ? up to 45 bidirectional i/o lines ? dual pin-shared external interrupts
rev. 1.00 8 ???i? 0?? ?01? rev. 1.00 9 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? multiple timer modules for time measurement, input capture, compare match output or pwm output or single pulse output function 2 compact type 10-bit timer module - ctm 1 standard type 10-bit timer module - stm 1 standard type 16-bit timer module - stm ? serial interface modules with dual spi and i 2 c interfaces ? single serial spi interface ? dual comparator functions ? dual time-base functions for generation of fxed time interrupt signals ? up to 16 channel 12-bit resolution a/d converter ? low voltage reset function ? low voltage detect function ? flash program memory can be re-programmed up to 1,000,000 times ? flash program memory data retention > 10 years ? support in system programing function - isp ? wide range of available package types ? partial lock function general description the HT66FB540, ht66fb550 and ht66fb560 are flash memory a/d with usb type 8-bit high performance risc architecture microcontrollers, designed for applications that interface directly to analog signals and which require an usb interface. offering users the convenience of flash memory multi-programming features, these devices also include a wide range of functions and features. other memory includes an area of ram data memory. analog features include a multi-channel 12-bit a/d converter and dual comparator functions. multiple and extremely flexible timer modules provide timing, pulse generation and pwm generation functions. communication with the outside world is catered for by including fully integrated spi, i 2 c and usb interface functions, three popular interfaces which provide designers with a means of easy communication with external peripheral hardware. protective features such as an internal watchdog timer, low voltage reset and low voltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. the external interrupt can be triggered with falling edges or both falling and rising edges. a full choice of four oscillator functions are provided including two fully integrated system oscillators which requires no external components for their implementation. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimize microcontroller operation and minimize power consumption. the inclusion of fexible i/o programming features, time-base functions along with many other features ensure that these devices will find specific excellent use in a wide range of application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. these devices are fully supported by the holtek range of fully functional development and programming tools, providing a means for fast and effcient product development cycles.
rev. 1.00 10 ???i? 0?? ?01? rev. 1.00 11 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi selection table most features are common to all devices, the main feature distinguishing them are program memory capacity, i/o count, ad channels, stack capacity and package types. the following table summarises the main features of each device. part no. v dd program memory data memory i/o external interrupt a/d timer module sim (spi/i 2 c) spi stack package HT66FB540 ?.?v~ 5.5v 4k16 51?8 ?5 ? 1?-bit 8 10-bit ctm?? 10-bit stm1? 16-bit stm1 8 ?8ssop 48lqfp ht66fb550 ?.?v~ 5.5v 8k16 7688 ?7 ? 1?-bit 16 10-bit ctm?? 10-bit stm1? 16-bit stm1 8 ?8ssop 40qfn 48lqfp ht66fb560 ?.?v~ 5.5v 16k16 10?48 45 ? 1?-bit 16 10-bit ctm?? 10-bit stm1? 16-bit stm1 1? 40qfn 48/64lqfp block diagram flash programming circuitry (icp) watchdog timer 8-bit risc mcu core reset circuit interrupt controller hxt oscillator 12-bit a/d converter lirc/lxt oscillator hirc oscillator stack flash program memory ram data memory spi tm0 low voltage reset low voltage detect tm1 tmn comparators tb0/tb1 i/o sim usb 2.0 full speed engine usb 2.0 xcvr 3.3v regulator
rev. 1.00 10 ???i? 0?? ?01? rev. 1.00 11 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi pin assignment HT66FB540 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 15 16 17 18 19 ?0 ?1 ?? ?? ?4 ?5 ?6 ?7 ?8 ?9 ?0 ?1 ?? ?? ?4 ?5 ?6 45 46 47 48 ?7 ?8 ?9 40 41 4? 4? 44 ht 66fb 540 48 lqfp - a n c pe4 / xt ? p?0 / tck 1 / ocdsd? udn/ gpio 0 udp / gpio 1 v ?? o ubus / pe 1 / ?vdd / vdd hvdd vss pe ? / xt 1 pe ? res / ocdsck pb 0 / sdo / sd? / ?n 0 n c n c p d 5 / t p 1 _ 1 p d 4 / t c k ? p d ? p d ? / t c k ? p d 1 / t p ? _ 1 / o s c ? p d 0 / t p ? _ 1 / o s c 1 pb 4 / tp 0 _ 1 / ?n 4 pb ? / scs / ?n ? pb ? / sck / ?n ? pb 1 / sdi / scl / ?n 1 n c n c n c nc pb6 / int 1 / ?n 6 pb5 / pck / ?n 5 nc nc nc n c n c n c n c p ? 7 / i n t 0 / ? n 7 p ? 6 / t c k 0 / c 1 - p ? 5 / t p 1 _ 0 / c 1 + p ? 4 / s c s ? / t p 0 _ 0 / c 1 x p ? ? / s c k ? / c 0 - p ? ? / s d i ? / c 0 + p e 0 / v d d i o / v r e f nc p ? 1 / s d o ? / c 0 x nc ht 66 fb 540 28 ssop - a ?8 ?7 ?6 ?5 ?4 ?? ?? ?1 ?0 19 18 17 16 15 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 p? 6 / tck 0 / c 1 - p? 5 / tp 1 _ 0 / c 1 + p? 4 / scs? / tp 0 _ 0 / c 1 x p? ? / sck? / c 0 - p? 7 / int 0 / ?n 7 pb 6 / int 1 / ?n 6 pb 5 / pck / ?n 5 pb 4 / tp 0 _ 1 / ?n 4 pb ? / scs / ?n ? pb ? / sck / ?n ? pb 1 / sdi / scl / ?n 1 pb 0 / sdo / sd? / ?n 0 pd 1 / tp ? _ 1 / osc ? pd 0 / tp ? _ 1 / osc 1 pe 0 / vddio / vref p? ? / sdi? / c 0 + p? 1 / sdo? / c 0 x p? 0 / tck 1 / ocdsd? udn / gpio 0 udp / gpio 1 v ??o ubus / pe 1 / ?vdd / vdd hvdd pe ? vss res / ocdsck pe4 / xt ? pe ? / xt 1
rev. 1.00 1? ???i? 0?? ?01? rev. 1.00 1? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ht66fb550 ht 66 fb 550 28 ssop - a ?8 ?7 ?6 ?5 ?4 ?? ?? ?1 ?0 19 18 17 16 15 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 p?6 / tck 0 / c 1 - p?5 / tp 1 _ 0 / c 1 + p?4 / scs? / tp 0 _ 0 / c 1 x p?? / sck? / c 0 - p?7 / int 0 / ?n 7 pb6 / int 1 / ?n 6 pb5 / pck / ?n 5 pb4 / tp 0 _ 1 / ?n 4 pb? / scs / ?n ? pb? / sck / ?n ? pb1 / sdi / scl / ?n 1 pb0 / sdo / sd? / ?n 0 pd 1 / tp ? _ 1 / osc ? pd 0 / tp ? _ 1 / osc 1 pe 0 / vddio / vref p? ? / sdi? / c 0 + p?1 / sdo? / c 0 x p?0 / tck 1 / ocdsd? udn/ gpio 0 udp / gpio 1 v ?? o ubus / pe 1 / ?vdd / vdd hvdd pe ? vss res / ocdsck pe 4 / xt ? pe ? / xt 1 ht 66fb 550 40 qfn - a 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 15 16 17 18 19 ?0 ?1 ?? ?? ?4 ?5 ?6 ?7 ?8 ?9 ?0 ?1 ?? ?? ?4 ?5 ?6 ?7 ?8 ?9 40 p? 0 / tck 1 / ocdsd? udn / gpio 0 udp / gpio 1 v ??o ubus / pe 1 / ?vdd / vdd hvdd vss pe ? / xt 1 pe 4 / xt ? p b 0 / s d o / s d ? / ? n 0 p d 6 / t p ? _ 0 p d 5 / t p 1 _ 1 p d 4 / t c k ? p d ? p d ? / t c k ? p d 1 / t p ? _ 1 / o s c ? p d 0 / t p ? _ 1 / o s c 1 p e ? p b 1 / s d i / s c l / ? n 1 pc ? / ?n 10 pc 1 / ?n 9 pc 0 / ?n 8 pb 7 pb 6 / int 1 / ?n 6 pb 5 / pck / ?n 5 pb 4 / tp 0 _ 1 / ?n 4 pb ? / scs / ?n ? pb ? / sck / ?n ? pc 5 / ?n 1? p c 6 / ? n 1 4 p c 7 / ? n 1 5 p ? 7 / i n t 0 / ? n 7 p ? 6 / t c k 0 / c 1 - p ? 5 / t p 1 _ 0 / c 1 + p ? 4 / s c s ? / t p 0 _ 0 / c 1 x p ? ? / s c k ? / c 0 - p ? ? / s d i ? / c 0 + p e 0 / v d d i o / v r e f res / ocdsck p ? 1 / s d o ? / c 0 x 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 15 16 17 18 19 ?0 ?1 ?? ?? ?4 ?5 ?6 ?7 ?8 ?9 ?0 ?1 ?? ?? ?4 ?5 ?6 45 46 47 48 ?7 ?8 ?9 40 41 4? 4? 44 ht 66 fb 550 48 lqfp - a p e 5 pe 4 / xt ? p? 0 / tck 1 / ocdsd? udn / gpio 0 udp / gpio 1 v ?? o ubus / pe1 / ?vdd / vdd hvdd vss pe? / xt 1 pe? res / ocdsck pb 0 / sdo / sd? / ?n 0 p d 7 / t p ? _ 0 p d 6 / t p ? _ 0 p d 5 / t p 1 _ 1 p d 4 / t c k ? p d ? p d ? / t c k ? p d 1 / t p ? _ 1 / o s c ? p d 0 / t p ? _ 1 / o s c 1 pb 4 / tp 0 _ 1 / ?n 4 pb ? / scs / ?n ? pb ? / sck / ?n ? pb 1 / sdi / scl / ?n 1 n c n c n c pb 7 pb 6 / int 1 / ?n 6 pb 5 / pck / ?n 5 pc 1 / ?n 9 pc 0 / ?n 8 pc ? / ?n 10 p c 4 / ? n 1 ? p c 5 / ? n 1 ? p c 6 / ? n 1 4 p c 7 / ? n 1 5 p ? 7 / i n t 0 / ? n 7 p ? 6 / t c k 0 / c 1 - p ? 5 / t p 1 _ 0 / c 1 + p ? 4 / s c s ? / t p 0 _ 0 / c 1 x p ? ? / s c k ? / c 0 - p ? ? / s d i ? / c 0 + p e 0 / v d d i o / v r e f nc p ? 1 / s d o ? / c 0 x pc ? / ?n 11
rev. 1.00 1? ???i? 0?? ?01? rev. 1.00 1? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ht66fb560 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 15 16 17 18 19 ?0 ?1 ?? ?? ?4 ?5 ?6 ?7 ?8 ?9 ?0 ?1 ?? ?? ?4 ?5 ?6 45 46 47 48 ?7 ?8 ?9 40 41 4? 4? 44 ht 66fb 560 48 lqfp - a p e 5 pe 4 / xt ? p? 0 / tck 1 / ocdsd? udn / gpio 0 udp / gpio 1 v ?? o ubus / pe1 / ?vdd / vdd hvdd vss pe ? / xt 1 pe ? res / ocdsck pb 0 / sdo / sd? / ?n 0 p d 7 / t p ? _ 0 p d 6 / t p ? _ 0 p d 5 / t p 1 _ 1 p d 4 / t c k ? p d ? p d ? / t c k ? p d 1 / t p ? _ 1 / o s c ? p d 0 / t p ? _ 1 / o s c 1 pb 4 / tp 0 _ 1 / ?n 4 pb ? / scs / ?n ? pb ? / sck / ?n ? pb 1 / sdi / scl / ?n 1 n c n c n c pb 7 pb 6 / int 1 / ?n 6 pb 5 / pck / ?n 5 pc 1 / ?n 9 pc 0 / ?n 8 pc ? / ?n 10 p c 4 / ? n 1 ? p c 5 / ? n 1 ? p c 6 / ? n 1 4 p c 7 / ? n 1 5 p ? 7 / i n t 0 / ? n 7 p ? 6 / t c k 0 / c 1 - p ? 5 / t p 1 _ 0 / c 1 + p ? 4 / s c s ? / t p 0 _ 0 / c 1 x p ? ? / s c k ? / c 0 - p ? ? / s d i ? / c 0 + p e 0 / v d d i o / v r e f nc p ? 1 / s d o ? / c 0 x pc ? / ?n 11 p ? 1 / s d o ? / c 0 x ht 66 fb 560 64 lqfp - a 1 ? ? 4 5 6 7 8 9 10 11 1? 1? ?0 ?1 ?? ?? ?4 ?5 ?6 ?7 ?8 60 61 6? 6? 64 ?9 ?0 ?1 ?? 5? 5? 54 55 56 57 58 59 14 15 16 4? 44 45 46 47 48 ?6 ?7 ?8 ?9 40 41 4? ?? ?4 ?5 17 18 19 49 50 51 pb 0 / sdo / sd? / ?n 0 pb 7 pb 6 / int 1 / ?n 6 pb 5 / pck / ?n 5 pb 4 / tp 0 _ 1 / ?n 4 pb ? / scs / ?n ? pb ? / sck / ?n ? pb 1 / sdi / scl / ?n 1 pf 7 pc 1 / ?n 9 pc 0 / ?n 8 n c p c 4 / ? n 1 ? p c 5 / ? n 1 ? p c 6 / ? n 1 4 p c 7 / ? n 1 5 p ? 7 / i n t 0 / ? n 7 p ? 6 / t c k 0 / c 1 - p ? 5 / t p 1 _ 0 / c 1 + p ? 4 / s c s ? / t p 0 _ 0 / c 1 x p ? ? / s c k ? / c 0 - p ? ? / s d i ? / c 0 + p d 7 / t p ? _ 0 p d 6 / t p ? _ 0 p d 5 / t p 1 _ 1 p d 4 / t c k ? p d ? p d ? / t c k ? p d 1 / t p ? _ 1 / o s c ? p d 0 / t p ? _ 1 / o s c 1 p f ? p f ? p f 1 p f 0 p f 4 pe 4 / xt ? pe? / xt 1 nc udn / gpio 0 udp / gpio 1 v ?? o ubus / pe1 / ?vdd / vdd hvdd pe? vss res / ocdsck p e 5 nc nc p f 5 pc ? / ?n 11 pc ? / ?n 10 nc p ? 0 / t c k 1 / o c d s d ? n c p e 0 / v d d i o / v r e f nc nc nc p f 6 nc nc n c ht 66 fb 560 40 qfn - a 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 15 16 17 18 19 ?0 ?1 ?? ?? ?4 ?5 ?6 ?7 ?8 ?9 ?0 ?1 ?? ?? ?4 ?5 ?6 ?7 ?8 ?9 40 p?0 / tck 1 / ocdsd? udn/ gpio 0 udp / gpio 1 v ?? o ubus / pe 1 / ?vdd / vdd hvdd vss pe ? / xt 1 pe 4 / xt ? p b 0 / s d o / s d ? / ? n 0 p d 6 / t p ? _ 0 p d 5 / t p 1 _ 1 p d 4 / t c k ? p d ? p d ? / t c k ? p d 1 / t p ? _ 1 / o s c ? p d 0 / t p ? _ 1 / o s c 1 p e ? p b 1 / s d i / s c l / ? n 1 pc ? / ?n 10 pc 1 / ?n 9 pc 0 / ?n 8 pb 7 pb 6 / int 1 / ?n 6 pb 5 / pck / ?n 5 pb 4 / tp 0 _ 1 / ?n 4 pb ? / scs / ?n ? pb ? / sck / ?n ? pc 5 / ?n 1? p c 6 / ? n 1 4 p c 7 / ? n 1 5 p ? 7 / i n t 0 / ? n 7 p ? 6 / t c k 0 / c 1 - p ? 5 / t p 1 _ 0 / c 1 + p ? 4 / s c s ? / t p 0 _ 0 / c 1 x p ? ? / s c k ? / c 0 - p ? ? / s d i ? / c 0 + p e 0 / v d d i o / v r e f res / ocdsck p ? 1 / s d o ? / c 0 x
rev. 1.00 14 ???i? 0?? ?01? rev. 1.00 15 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi pin description the pins on these devices can be referenced by their port name, e.g. pa.0, pa.1 etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other functions such as the analog to digital converter, serial port pins etc. the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. HT66FB540 pin name function opt i/t o/t description p ?0/tck1/ocdsd? p? 0 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tck1 st tm1 in?ut ocdsd? st cmos debug data i/o in on - chi? debug su??o?t mode p ?1/sdo?/c0x p? 1 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sdo? cmos spi? data out?ut c0x cmos com?a?ato? 0 out?ut p ??/sdi?/c0+ p ?? p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sdi? st spi? data in?ut c0+ ?n com?a?ato? 0 ?ositive in?ut p ??/sck?/c0- p ?? p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sck? st nmos spi? se?ia? c?ock c0- ?n com?a?ato? 0 negative in?ut p ?4/ scs? /tp0_0/c1x p? 4 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? scs? st cmos spi? s?ave se?ect tp0_0 tmpc0 st cmos tm0 i/o c1x cmos com?a?ato? 1 out?ut p ?5/tp1_0/c1+ p? 5 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp1_0 tmpc0 st cmos tm1 i/o c1+ ?n com?a?ato? 1 ?ositive in?ut p ?6/tck0/c1- p? 6 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tck0 st tm0 in?ut c1- ?n com?a?ato? 1 negative in?ut p ?7/int0/?n7 p? 7 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? int0 st exte?na? inte??u?t 0 ?n7 ?cer0 ?n ?/d channe? 7 pb0/sdo/sd?/?n0 pb0 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sdo cmos spi data out?ut sd? st nmos i ? c data ?n0 ?cer0 ?n ?/d channe? 0 pb1/sdi/scl/?n1 pb1 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sdi st spi data in?ut scl st nmos i ? c c?ock ?n1 ?cer0 ?n ?/d channe? 1
rev. 1.00 14 ???i? 0?? ?01? rev. 1.00 15 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi pin name function opt i/t o/t description pb?/sck/?n? pb? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sck st cmos spi se?ia? c?ock ?n? ?cer0 ?n ?/d channe? ? pb?/ scs /?n? pb? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? scs st cmos spi s?ave se?ect ?n? ?cer0 ?n ?/d channe? ? pb4/tp0_1/?n4 pb4 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp0_1 tmpc0 st cmos tm0 i/o ?n4 ?cer0 ?n ?/d channe? 4 pb5/pck/?n5 pb5 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pck cmos pe?i?he?a? out?ut c?ock ?n5 ?cer0 ?n ?/d channe? 5 pb6/int1/?n6 pb6 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? int1 st exte?na? inte??u?t 1 ?n6 ?cer0 ?n ?/d channe? 6 pd0/tp?_1/osc1 pd0 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp?_1 tmpc1 st cmos tm? i/o osc1 hxt hxt ?in pd1/tp?_1/osc? pd1 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp?_1 tmpc1 st cmos tm? i/o osc? hxt hxt ?in pd?/tck? pd? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tck? st tm? in?ut pd? pd? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pd4/tck? pd4 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tck? tmpc1 st tm? in?ut pd5/tp1_1 pd5 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp1_1 tmpc0 st cmos tm1 i/o pe0/vddio/vref pe0 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? vddio pwr p ? exte?na? ?owe? in?ut vref ?n ?dc ?efe?ence ?owe? in?ut pe1/ubus pe1 st gene?a? ?u??ose i/o. in?ut on?y ubus pwr usb sie vdd pe? pe? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pe?/xt1 pe? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? xt1 co lxt lxt ?in pe4/xt? pe4 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? xt? co lxt lxt ?in
rev. 1.00 16 ???i? 0?? ?01? rev. 1.00 17 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi pin name function opt i/t o/t description res /ocdsck res co st reset in?ut ocdsck st debug c?ock in?ut in on-chi? debug su??o?t mode udn/gpio0 udn st cmos usb udn ?ine gpio0 st cmos gene?a? ?u??ose i/o udp/gpio1 udp st cmos usb udp ?ine gpio1 st cmos gene?a? ?u??ose i/o vdd/? vdd vdd/ ? vdd pwr powe? su???y vss/? vss vss/ ? vss pwr g?ound v??o v??o pwr ?.?v ?egu?ato? out?ut hvdd hvdd pwr hirc osci??ato? positive powe? su???y note: i/t: input type; o/t: output type opt: optional by confguration option (co) or register option pwr: power; co: confguration option st: schmitt trigger input; cmos: cmos output; hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator an: analog input pin where devices exist in more than one package type the table refects the situation for the package with the largest number of pins. for this reason not all pins described in the table may exist on all package types.
rev. 1.00 16 ???i? 0?? ?01? rev. 1.00 17 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ht66fb550 pin name function opt i/t o/t description p ?0/tck1/ocdsd? p? 0 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tck1 st tm1 in?ut ocdsd? st cmos debug data i/o in on-chi? debug su??o?t mode p ?1/sdo?/c0x p? 1 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sdo? cmos spi? data out?ut c0x cmos com?a?ato? 0 out?ut p ??/sdi?/c0+ p ?? p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sdi? st spi? data in?ut c0+ ?n com?a?ato? 0 ?ositive in?ut p ??/sck?/c0- p ?? p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sck? st nmos spi? se?ia? c?ock c0- ?n com?a?ato? 0 negative in?ut p ?4/ scs? /tp0_0/ c1x p? 4 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? scs? st cmos spi? s?ave se?ect tp0_0 tmpc0 st cmos tm0 i/o c1x cmos com?a?ato? 1 out?ut p ?5/tp1_0/c1+ p? 5 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp1_0 tmpc0 st cmos tm1 i/o c1+ ?n com?a?ato? 1 ?ositive in?ut p ?6/tck0/c1- p? 6 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tck0 st tm0 in?ut c1- ?n com?a?ato? 1 negative in?ut p ?7/int0/?n7 p? 7 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? int0 st exte?na? inte??u?t 0 ?n7 ?cer0 ?n ?/d channe? 7 pb0/sdo/sd?/?n0 pb0 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sdo cmos spi data out?ut sd? st nmos i ? c data ?n0 ?cer0 ?n ?/d channe? 0 pb1/sdi/scl/?n1 pb1 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sdi st spi data in?ut scl st nmos i ? c c?ock ?n1 ?cer0 ?n ?/d channe? 1 pb?/sck/?n? pb? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sck st cmos spi se?ia? c?ock ?n? ?cer0 ?n ?/d channe? ? pb?/ scs /?n? pb? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? scs st cmos spi s?ave se?ect ?n? ?cer0 ?n ?/d channe? ?
rev. 1.00 18 ???i? 0?? ?01? rev. 1.00 19 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi pin name function opt i/t o/t description pb4/tp0_1/?n4 pb4 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp0_1 tmpc0 st cmos tm0 i/o ?n4 ?cer0 ?n ?/d channe? 4 pb5/pck/?n5 pb5 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pck cmos pe?i?he?a? out?ut c?ock ?n5 ?cer0 ?n ?/d channe? 5 pb6/int1/?n6 pb6 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? int1 st exte?na? inte??u?t 1 ?n6 ?cer0 ?n ?/d channe? 6 pb7 pb7 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pc0/?n8 pc0 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? ?n8 ?cer1 ?n ?/d channe? 8 pc1/?n9 pc1 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? ?n9 ?cer1 ?n ?/d channe? 9 pc?/?n10 pc? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? ?n10 ?cer1 ?n ?/d channe? 10 pc?/? n11 pc? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? ? n11 ?cer1 ?n ?/d channe? 11 pc4/?n1? pc4 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? ?n1? ?cer1 ?n ?/d channe? 1? pc5/?n1? pc5 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? ?n1? ?cer1 ?n ?/d channe? 1? pc6/?n14 pc6 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? ?n14 ?cer1 ?n ?/d channe? 14 pc7/?n15 pc7 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? ?n15 ?cer1 ?n ?/d channe? 15 pd0/tp?_1/osc1 pd0 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp?_1 tmpc1 st cmos tm? i/o osc1 hxt hxt ?in pd1/tp?_1/osc? pd1 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp?_1 tmpc1 st cmos tm? i/o osc? hxt hxt ?in pd?/tck? pd? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tck? st tm? in?ut pd? pd? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pd4/tck? pd4 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tck? tmpc1 st tm? in?ut
rev. 1.00 18 ???i? 0?? ?01? rev. 1.00 19 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi pin name function opt i/t o/t description pd5/tp1_1 pd5 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp1_1 tmpc0 st cmos tm1 i/o pd6/tp?_0 pd6 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp?_0 tmpc1 st cmos tm? i/o pd7/tp?_0 pd7 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp?_0 tmpc1 st cmos tm? i/o pe0/vddio/vref pe0 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? vddio pwr p ? exte?na? ?owe? in?ut vref ?n ?dc ?efe?ence ?owe? in?ut pe1/ubus pe1 st gene?a? ?u??ose i/o. in?ut on?y ubus pwr pwr usb sie vdd pe? pe? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pe?/xt1 pe? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? xt1 co lxt lxt ?in pe4/xt? pe4 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? xt? co lxt lxt ?in pe5 pe5 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? res /ocdsck res co st reset in?ut ocdsck st debug c?ock in?ut in on-chi? debug su??o?t mode udn/gpio0 udn st cmos usb udn ?ine gpio0 st cmos gene?a? ?u??ose i/o udp/gpio1 udp st cmos usb udp ?ine gpio1 st cmos gene?a? ?u??ose i/o vdd/? vdd vdd/ ? vdd pwr powe? su???y vss/? vss vss/ ? vss pwr g?ound v??o v??o pwr ?.?v ?egu?ato? out?ut hvdd hvdd pwr hirc osci??ato? positive powe? su??? y. note: i/t: input type; o/t: output type opt: optional by confguration option (co) or register option pwr: power; co: confguration option st: schmitt trigger input; cmos: cmos output; hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator an: analog input pin where devices exist in more than one package type the table refects the situation for the package with the largest number of pins. for this reason not all pins described in the table may exist on all package types.
rev. 1.00 ?0 ???i? 0?? ?01? rev. 1.00 ?1 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ht66fb560 pin name function opt i/t o/t description p ?0/tck1/ocdsd? p? 0 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tck1 st tm1 in?ut ocdsd? st cmos debug data i/o in on-chi? debug su??o?t mode p ?1/sdo?/c0x p? 1 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sdo? cmos spi? data out?ut c0x cmos com?a?ato? 0 out?ut p ??/sdi?/c0+ p ?? p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sdi? st spi? data in?ut c0+ ?n com?a?ato? 0 ?ositive in?ut p ??/sck?/c0- p ?? p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sck? st nmos spi? se?ia? c?ock c0- ?n com?a?ato? 0 negative in?ut p ?4/ scs? /tp0_0/c1x p? 4 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? scs? st cmos spi? s?ave se?ect tp0_0 tmpc0 st cmos tm0 i/o c1x cmos com?a?ato? 1 out?ut p ?5/tp1_0/c1+ p? 5 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp1_0 tmpc0 st cmos tm1 i/o c1+ ?n com?a?ato? 1 ?ositive in?ut p ?6/tck0/c1- p? 6 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tck0 st tm0 in?ut c1- ?n com?a?ato? 1 negative in?ut p ?7/int0/?n7 p? 7 p ?pu p? wu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? int0 st exte?na? inte??u?t 0 ?n7 ?cer0 ?n ?/d channe? 7 pb0/sdo/sd?/?n0 pb0 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sdo cmos spi data out?ut sd? st nmos i ? c data ?n0 ?cer0 ?n ?/d channe? 0 pb1/sdi/scl/?n1 pb1 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sdi st spi data in?ut scl st nmos i ? c c?ock ?n1 ?cer0 ?n ?/d channe? 1 pb?/sck/?n? pb? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? sck st cmos spi se?ia? c?ock ?n? ?cer0 ?n ?/d channe? ?
rev. 1.00 ?0 ???i? 0?? ?01? rev. 1.00 ?1 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi pin name function opt i/t o/t description pb?/ scs /?n? pb? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? scs st cmos spi s?ave se?ect ?n? ?cer0 ?n ?/d channe? ? pb4/tp0_1/?n4 pb4 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp0_1 tmpc0 st cmos tm0 i/o ?n4 ?cer0 ?n ?/d channe? 4 pb5/pck/?n5 pb5 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pck cmos pe?i?he?a? out?ut c?ock ?n5 ?cer0 ?n ?/d channe? 5 pb6/int1/?n6 pb6 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? int1 st exte?na? inte??u?t 1 ?n6 ?cer0 ?n ?/d channe? 6 pb7 pb7 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pc0/?n8 pc0 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? ?n8 ?cer1 ?n ?/d channe? 8 pc1/?n9 pc1 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? ?n9 ?cer1 ?n ?/d channe? 9 pc?/?n10 pc? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? ?n10 ?cer1 ?n ?/d channe? 10 pc?/? n11 pc? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? ? n11 ?cer1 ?n ?/d channe? 11 pc4/?n1? pc4 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u?. ?n1? ?cer1 ?n ?/d channe? 1? pc5/?n1? pc5 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? ?n1? ?cer1 ?n ?/d channe? 1? pc6/?n14 pc6 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? ?n14 ?cer1 ?n ?/d channe? 14 pc7/?n15 pc7 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? ?n15 ?cer1 ?n ?/d channe? 15 pd0/tp?_1/osc1 pd0 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp?_1 tmpc1 st cmos tm? i/o osc1 hxt hxt ?in pd1/tp?_1/osc? pd1 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp?_1 tmpc1 st cmos tm? i/o osc? hxt hxt ?in
rev. 1.00 ?? ???i? 0?? ?01? rev. 1.00 ?? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi pin name function opt i/t o/t description pd?/tck? pd? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tck? st tm? in?ut pd? pd? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pd4/tck? pd4 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tck? tmpc1 st tm? in?ut pd5/tp1_1 pd5 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp1_1 tmpc0 st cmos tm1 i/o pd6/tp?_0 pd6 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp?_0 tmpc1 st cmos tm? i/o pd7/tp?_0 pd7 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? tp?_0 tmpc1 st cmos tm? i/o pe0/vddio/vref pe0 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? vddio pwr p ? exte?na? ?owe? in?ut vref ?n ?dc ?efe?ence ?owe? in?ut pe1/ubus pe1 st gene?a? ?u??ose i/o. in?ut on?y ubus pwr pwr usb sie vdd pe? pe? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pe?/xt1 pe? pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? xt1 co lxt lxt ?in pe4/xt? pe4 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? xt? co lxt lxt ?in pe5 pe5 pxpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pf0 pf0 pfpu pxwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u?. pf1 pf1 pfpu pfwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pf? pf? pfpu pfwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pf? pf? pfpu pfwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pf4 pf4 pfpu pfwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pf5 pf5 pfpu pfwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pf6 pf6 pfpu pfwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u? pf7 pf7 pfpu pfwu st cmos gene?a? ?u??ose i/o. registe? enab?ed ?u??-u? and wake-u?
rev. 1.00 ?? ???i? 0?? ?01? rev. 1.00 ?? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi pin name function opt i/t o/t description res /ocdsck res co st reset in?ut ocdsck st debug c?ock in?ut in on-chi? debug su??o?t mode udn/gpio0 udn st cmos usb udn ?ine gpio0 st cmos gene?a? ?u??ose i/o udp/gpio1 udp st cmos usb udp ?ine gpio1 st cmos gene?a? ?u??ose i/o vdd/? vdd vdd/ ? vdd pwr powe? su???y vss/? vss vss/ ? vss pwr g?ound v??o v??o pwr ?.?v ?egu?ato? out?ut hvdd hvdd pwr hirc osci??ato? positive powe? su???y note: i/t: input type; o/t: output type opt: optional by confguration option (co) or register option pwr: power; co: confguration option st: schmitt trigger input; cmos: cmos output; hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator an: analog input pin where devices exist in more than one package type the table refects the situation for the package with the largest number of pins. for this reason not all pins described in the table may exist on all package types. absolute maximum ratings supply voltage ................................................................................................ v ss ?0.3v to v ss +6.0v input voltage .................................................................................................. v ss ? 0.3v to v dd +0.3v storage temperature ................................................................................................... -50 c to 125c operating temperature ................................................................................................. -40 c to 85 c i oh total .................................................................................................................................. -100ma i ol total ................................................................................................................................... 150ma total power dissipation ........................................................................................................ 500mw note: these are stress ratings only. stresses exceeding the range specified under "absolute maximum ratings" may cause substantial damage to these devices. functional operation of these devices at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect devices reliability.
rev. 1.00 ?4 ???i? 0?? ?01? rev. 1.00 ?5 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi d.c. characteristics ta=2 5 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd1 o?e? ating vo?tage (c?ysta? osc) f sys =4mhz ?.? 5.5 v f sys =6mhz ?.? 5.5 v f sys =8mhz ?.? 5.5 v f sys =1?mhz ?.7 5.5 v f sys =16mhz 4.5 5.5 v v dd? o?e? ating vo?tage (high f?equency inte?na? rc osc) f sys =1?mhz ?.7 5.5 v i dd1 o?e?ating cu??ent (c?ysta? osc? f sys =f h ? f s =f sub =f lxt o? f lirc ) ?v no ?oad? f h =4mhz? ? dc off? wdt enab?e 0.8 1.5 m? 5v 1.8 4.0 m? ?v no ?oad? f h =6mhz? ? dc off? wdt enab?e 1.0 ?.0 m? 5v ?.5 5.0 m? ?v no ?oad? f h =8mhz? ? dc off? wdt enab?e 1.? ?.0 m? 5v ?.0 5.5 m? ?v no ?oad? f h =1?mhz? ? dc off? wdt enab?e ?.0 4.0 m? 5v 4.0 7.0 m? i dd? o?e?ating cu??ent (hirc osc? f sys =f h ? f s =f sub =f lxt o? f lirc ) ?v no ?oad? f h =1?mhz? ? dc off? wdt enab?e ?.0 4.0 m? 5v 4.0 7.0 m? i dd? o?e?ating cu??ent (lxt osc ? f sys =f l =f lxt ? f s =f sub =f lxt ) ?v no ?oad? ? dc off? wdt enab?e. lvr enab ?e 40 80 5v 70 150 i dd4 o?e?ating cu??ent (lirc osc? f sys =f l =f lirc ? f s =f sub =f lirc ) ?v no ?oad? ? dc off? wdt enab?e? lvr enab ?e? f lirc =??khz 40 80 5v 70 150 i dd5 o?e?ating cu??ent (hirc osc? f sys =f h ? f s =f sub =f lxt o? f lirc ) ?v no ?oad? f h =1?mhz? ? dc off? wdt enab?e? usb enab?e? pll on? v??o on 5.5 10.0 m? 5v 11 16 m? i dd6 o?e?ating cu??ent (c?ysta? osc? f sys =f h ? f s =f sub =f lirc ) 5v no ?oad? f h =6mhz? ? dc off? wdt enab?e? usb enab?e? pll on? v??o on 10 15 m? 5v no ?oad? f h =1?mhz? ? dc off? wdt enab?e? usb enab?e? pll on? v??o on 11 16 m? 5v no ?oad? f h =16mhz? ? dc off? wdt enab?e? usb enab?e? pll on? v??o on 1? 17 m? i stb1 stanby cu??ent (id?e 1) (c?ysta? osc? f sys =f h ? f s =f sub =f lxt o? f lirc ) ?v no ?oad? system h? lt ? ? dc off? wdt enab?e? f sys =osci??ato? on (fsyson=1) 0.8 1.5 m? 5v 1.5 ?.0 m? i stb? stanby cu??ent (id?e 0) (c?ysta? o? hirc osc? f sys =off ? f s =f sub =f lxt o? f lirc ) ?v no ?oad? system h? lt ? ? dc off? wdt enab?e? f sys =osci??ato? off (fsyson=0) 1.5 ?.0 5v ?.0 6.0 i stb? stanby cu??ent (id?e 0) (lxt osc ? f sys =off ? f s =f sub =f lxt ) ?v no ?oad? system h? lt ? ? dc off? wdt enab ?e ?.0 4.0 5v ?.5 7.0 i stb4 stanby cu??ent (id?e) (lirc osc? f sys =off ? f s =f sub =f lirc ) ?v no ?oad? system h? lt ? ? dc off? wdt enab ?e 1.5 ?.0 5v ?.0 6.0 i stb5 stanby cu??ent (s?ee? 0) (c?ysta? o? hirc osc? f sys =off ? f s =f sub =f lxt o? f lirc ) ?v no ?oad? system h? lt ? ? dc off? wdt disab ?e 0.1 1.0 5v 0.? ?.0
rev. 1.00 ?4 ???i? 0?? ?01? rev. 1.00 ?5 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi symbol parameter test conditions min. typ. max. unit v dd conditions i stb6 stanby cu??ent (s?ee? 1) (c?ysta? o? hirc osc? f sys =off ? f s =f sub =f lxt o? f lirc ) ?v no ?oad? system h? lt ? ? dc off? wdt enab ?e 1.5 ?.0 a 5v ?.0 6.0 a i stb7 stanby cu??ent (s?ee? 0) (c?ysta? o? hirc osc? f sys =off ? f s =f sub =f lxt o? f lirc ) no ?oad? system h? lt ? ? dc off? wdt disab ?e? lvr enab?e and lvden=1 60 90 a i sus1 sus?end cu??ent (s?ee? 0) (c?ysta? o? hirc osc? f sys =off ? f s =f sub =f lxt o? f lirc ) 5v no ?oad? system h? lt ? ? dc off? wdt disab ?e? usb t?ansceive ?? ?.?v regu?ato? on and c?? sus?end? (ucc.4) ?60 4?0 a i sus? sus?end cu??ent (s?ee? 0) (c?ysta? o? hirc osc? f sys =off ? f s =f sub =f lxt o? f lirc ) 5v no ?oad? system h? lt ? ? dc off? wdt disab ?e? usb t?ansceive ?? ?.?v regu?ato? on and set sus?end? (ucc.4) ?40 ??0 a v il1 in? ut low vo?tage fo? i/o po?ts? tck and int 0 0.?v dd v v ih1 in? ut high vo?tage fo? i/o po?ts? tck and int 0.8v dd v dd v v il? in? ut low vo?tage ( res ) 0 0.4v dd v v ih? in? ut high vo?tage ( res ) 0.9v dd v dd v i ol i/o po?t sink cu??ent ?v v ol =0.1v dd (p ?oi o? pxoi=1) 4 8 m? 5v v ol =0.1v dd (p ?oi o? pxoi=1) 10 ?0 m? 5v v ol =0.1v dd (p ?oi o? pxoi=0) ? 4 m? i oh i/o po?t? sou?ce cu??ent ?v v oh =0.9v dd (p ?oi o? pxoi=1) -? -4 m? 5v v oh =0.9v dd (p ?oi o? pxoi=1) -5 -10 m? 5v v oh =0.9v dd (p ?oi o? pxoi=0) -? -4 m? v v??o ?.?v ?egu?ato? out?ut 5v i v??o =70m? ?.0 ?.? ?.6 v r udp pu?? -high resistance of udp to v??o ?.?v -5% 1.5 +5% k r ph pu??-high resistance of i/o po?ts ?v ?0 60 100 k 5v 10 ?0 50 k r pl pu??-?ow resistance of ubus ?in 5v susp?=1? rubus=0 0.5 1 1.5 m
rev. 1.00 ?6 ???i? 0?? ?01? rev. 1.00 ?7 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi a.c. characteristics ta=2 5 c symbol parameter v dd condition min. typ. max. unit f sys1 system c?ock (c?ysta? osc) ?.?~5.5v ? 4 mhz ?.?~5.5v ? 6 mhz ?.?~5.5v ? 8 mhz ?.7~5.5v ? 1? mhz 4.5~5.5v ? 16 mhz f sys? system c?ock (hirc osc) ?.?~5.5v non-usb mode? ta= ? 5 c -?% 1? +?% mhz ?.0~5.5v non-usb mode? ta=-40~85 c -6% 1? +6% mhz ?.?~5.5v non-usb mode? ta=-40~85 c -10% 1? +10% mhz ?.?~5.5v usb mode -0.?5% 1? +0.?5% mhz f sys? system c?ock (??768 c?ysta?) ??768 hz f lirc system c?ock (??k rc) 5v ta= ?5 c -10% ?? +10% khz ?.?~5.5v ta=-40 c to 85 c -50% ?? +60% khz f timer time ? i/p f?equency (tmr) ?.?~5.5v ? 8 mhz ?.7~5.5v ? 1? mhz 4.5~5.5v ? 16 mhz t bgs vbg tu?n on stab?e time 10 ms t timer tckn in?ut pin minimum pu?se width 0.? v t res exte?na? reset minimum low pu?se width 10 v t int inte ??u? t minimum pu? se width 10 v t sst system sta?t-u? time? pe?iod (wake-u ? f?om h? lt ? f sys off at h ? lt state? 6orz0rgh:1rupdo0rgh 1rupdo0rgh:6orz0rgh f sys =hxt o ? lxt (s?ow mode no?ma? mode(hxt)? no?ma? mode s?ow mode(lxt)) 10?4 t sys f sys =hxt (wake-u ? f?om h? lt ? f sys off at h ? lt state) 10?4 t sys f sys =hirc 10?4 t sys f sys =lirc ? t sys system sta?t-u? time? pe?iod (wake-u ? f?om h? lt ? f sys on at h? lt state) ? t sys system sta?t-u? time? pe?iod (reset) 10?4 t sys t rstd system reset de? ay time (powe? on reset) ?5 50 100 ms system reset de? ay time (?ny reset exce?t powe? on reset) 8.? 16.7 ??.? ms
rev. 1.00 ?6 ???i? 0?? ?01? rev. 1.00 ?7 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi lvd & lvr electrical characteristics ta=2 5 c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr1 low vo ? tage reset vo?tage lvr enab ?e? ?.1v o?tion -5% ty ?. ?.1 +5% ty ?. v v lvr ? lvr enab ?e? ?.55v o?tion ?.55 v v lvr ? lvr enab ?e? ?.15v o?tion ?.15 v v lvr4 lvr enab ?e? ?.8v o?tion ?.8 v v lvd1 low vo ?tage detecto? vo?tage lvden=1 ? v lvd =?.0v -5% ty ?. ?.0 +5% ty ?. v v lvd ? lvden=1 ? v lvd =?.?v ?.? v v lvd ? lvden=1 ? v lvd =?.4v ?.4 v v lvd4 lvden=1 ? v lvd =?.7v ?.7 v v lvd5 lvden=1 ? v lvd =?.0v ?.0 v v lvd6 lvden=1 ? v lvd =?.?v ?.? v v lvd7 lvden=1 ? v lvd =?.6v ?.6 v v lvd8 lvden=1 ? v lvd =4.0v 4.0 v v bg refe? ence vo? tage with buffe? vo?tage -?% 1.?5 +?% v i bg ?dditiona? powe? consum?tion if refe? ence with buffe? is used ?00 ?00 i lvd ?dditiona? powe? consum?tion if lvd/lvr is used ?v lvd disab ?e lvd enab ?e (lvr enab ?e) ?0 45 5v 60 90 t lvr low vo ?tage width to reset 7 8 t lirc t lvr low vo ?tage width to reset 1?0 ?40 480 us t lvd low vo ?tage width to inte??u?t 1 ? t lirc t lvd low vo ?tage width to inte??u?t ?0 45 90 v t sreset softwa?e reset width to reset ? ? t lirc t sreset softwa?e reset width to reset 45 90 1?0 v t lvds lvdo stab ?e time fo? lvr enab?e? lvd off on 15 v
rev. 1.00 ?8 ???i? 0?? ?01? rev. 1.00 ?9 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi adc electrical characteristics ta=2 5 c symbol parameter v dd condition min. typ. max. unit ?v dd ?na?og o?e?ating vo?tage v ref = ?v dd ?.7 5.5 v v ?di ?/d in? ut vo?tage 0 v ref v v ref ?dc in?ut ?efe?ence vo?tage ?ange ?v dd =?v ?.0 ?v dd v ?v dd =5v ?.0 ?v dd v t ?dc ? /d conve? sion time ?.7~5.5v 1? bit ?dc 16 ?0 t ?d t ?dck ?/d conve?te? c?ock pe?iod ?.7~5.5v 0.5 10 v t on?st ?dc on to ?dc sta?t ?.7~5.5v 4 v dnl diffe ?entia? non-?inea?ity ?v/5v v ref = ?v dd -? +? lsb inl integ?a? non-?inea?ity ?v/5v v ref = ?v dd -4 +4 lsb i ?dc on?y ?dc enab?e? othe?s disab?e ?v no ?oad (t ?d v 1.0 ?.0 m? 5v no ?oad (t ?d v 1.5 ?.0 m? comparator electrical characteristics ta=2 5 c symbol parameter v dd condition min. typ. max. unit v cmp com?a?ato? o?e?ating vo?tage ?.? 5.5 v i cmp com?a?ato? o?e?ating cu??ent 5v ?00 i cstb com?a?ato? ?owe? down cu??ent 5v com?a?ato? disab?e 0.1 v cmpos com?a?ato? in? ut offset vo?tage 5v -10 +10 mv v hys hyste?esis width 5v ?0 40 60 mv v cm com?a?ato? common mode vo?tage ?ange v ss v dd -1.4v v ? ol com?a?ato? o?en ?oo? gain 60 80 db t pd com?a?ato? ?es?onse time ?v with 100mv ove?d?ive (note) ?00 400 ns 5v note: measured with comparator one input pin at v cm =(v dd -1.4)/2 while the other pin input transition from v ss to (v cm +100mv) or from v dd to (v cm -100mv). power on reset (ac+dc) electrical characteristics ta=2 5 c symbol parameter v dd condition min. typ. max. unit v por v dd sta? t vo?tage to ensu?e powe?-on reset 100 mv r por_?c v dd rise rate to ensu?e powe?-on reset 0.0?5 v/ms t por minimum time fo ? v dd stays at v por to ensu? e powe?-on reset 1 ms
rev. 1.00 ?8 ???i? 0?? ?01? rev. 1.00 ?9 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and fexibility. this makes these devices suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt, lxt, hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ? ? ? ? system clocking and pipelining
rev. 1.00 ?0 ???i? 0?? ?01? rev. 1.00 ?1 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter program counter high byte pcl register HT66FB540 pc11~pc8 pcl7~pcl0 ht66fb550 pc1?~pc8 ht66fb560 pc1?~pc8 program counter the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, which is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.00 ?0 ???i? 0?? ?01? rev. 1.00 ?1 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has multiple levels depending upon these devices and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost.
device stack levels HT66FB540/ht66fb550 8 ht66fb560 1? arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.00 ?? ???i? 0?? ?01? rev. 1.00 ?? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi flash program memory the program memory is the location where the user code or program is stored. for these devices series the program memory are flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. by using the appropriate programming tools, these flash devices offer users the fexibility to conveniently debug and develop their applications while also offering a means of feld programming and updating. structure the program memory has a capacity of 4k16 bits to 16k16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. device capacity banks HT66FB540 4k16 0 ht66fb550 8k16 0 ht66fb560 16k16 0? 1 the ht66fb560 has its program memory divided into two banks, bank 0 and bank 1. the required bank is selected using bit 5 of the bp register. special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 000h is reserved for use by these devices reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution.

program memory structure
rev. 1.00 ?? ???i? 0?? ?01? rev. 1.00 ?? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers defne the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the "tabrd [m]" or "tabrdl [m]" instructions, respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table.

table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is "1f00h" which refers to the start address of the last page within the 8k program memory of the ht66fb550. the table pointer is setup here to have an initial value of "06h". this will ensure that the frst data read from the data table will be at the program memory address "1f06h" or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the "tabrd [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "tabrd [m]" instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
rev. 1.00 ?4 ???i? 0?? ?01? rev. 1.00 ?5 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi partial lock the fash program partial lock function is used to protect a block of program memory. the fash program memory is divided into several blocks according to the program size. each block size is assigned by 512 words. the partial lock function is enabled by the partial lock confguration options. if the selected partial lock confguration option is selected, the corresponding partial lock function will be enabled and this block of program memory is unable to be accessed. any read operations will result in a value of 0000h. in this way, the user can select which block of the fash memory is to be protected. precautions should be taken when using the look-up table function in any locked blocks. the look-up table pointer is implemented by the tblp and tbhp registers. when the table pointer is setup to point to an address in an unlocked block, the table read instruction functions normally however when the pointer points to a locked block, there are two conditions: 1. if the table read instruction and the data table are located in the same block, then the table read instruction, tabrd [m], is valid. 2. if the table read instruction and the data table are located in different blocks, then the table read instruction is invalid. the read out data will be 0000h. the following example illustrates the basic operation of the partial lock function using the HT66FB540 as an example. if the last block is locked and if the table pointer address is setup to point to the last block, then if the table read instruction is executed in the last block, the data read back is valid. if the last block is locked, but the table pointer address points to the last page in other blocks, then when the table read instruction is executed, the read out data will be 0000h. t?brd locked inva?id 0000 h 01 ffh 0?00 h 0? ffh 0400 h 05 ffh 0600 h 07 ffh 0800 h 09 ffh 0 ? 00 h 0 bffh 0 c 00 h 0 dffh 0 e 00 h 0 fffh t?brd t?brd t?brd t?brd t?brd t?brd flash program memory ht 66fb 540 table read from different block the above example has the following setups: 1. enable the last page partial lock function via the confguration option. 2. write data 0f00h to the table pointer registers, tbhp and tblp. 3. table read instruction not located in locked block. 4. action: table read is invalid C data read back as 000h.
rev. 1.00 ?4 ???i? 0?? ?01? rev. 1.00 ?5 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi locked inva?id 0000 h 01 ffh 0?00 h 0? ffh 0400 h 05 ffh 0600 h 07 ffh 0800 h 09 ffh 0 ? 00 h 0 bffh 0 c 00 h 0 dffh 0 e 00 h 0 fffh t?brd flash program memory ht 66fb 540 table read from same block the above example has the following setups: 1. enable the last page partial lock function via the confguration option. 2. write data 0f00h to the table pointer registers, tbhp and tblp. 3. table read instruction is located in locked block. 4. action: table read instruction is valid. in system programming C isp the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-system using a two-line usb interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the devices. the program memory can be programmed serially in-system using the usb interface, namely using the udn and udp pins. the power is supplied by the ubus pin. the technical details regarding the in-system programming of these devices are beyond the scope of this document and will be supplied in supplementary literature. the flash program memory read/write function is implemented using a series of registers. flash memory read/write page size there are two page sizes, 32 words or 64 words, assigned for various flash memory size. when the flash memory, larger than 8k bytes, is selected, the 64 word page size is assigned per page and buffer. otherwise, the page and buffer size are assigned as 32 words.
rev. 1.00 ?6 ???i? 0?? ?01? rev. 1.00 ?7 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi the following diagram illustrates the read/write page and buffer assignment. the write buffer is controlled by the clwb bit in the frcr register. the clwb bit can be set high to enable the clear write buffer procedure, as the procedure is fnished, this bit will be cleared to low by hardware. the write buffer is flled when the fwen bit is set to high, when this bit is set high, the data in the write buffer will be written to the flash rom, the fwt bit is used to indicate the writing procedure. setting this bit high and check if the write procedure is fnished, this bit will be cleared by hardware. the read byte can be assigned by the address. the fden is used to enable the read function and the frd is used to indicate the reading procedure. when the reading procedure is fnished, this bit will be cleared by hardware. device page size (words) write buffer(words) HT66FB540(4k16) ?? ?? ht66fb550(8k16) ?? ?? ht66fb560(16k16) 64 64 w?ite buffe? clwb f?ash memo?y f?rh f?rl fd 0 h fd 0 l write one word to fd0l/fd0h f?ash memo?y f?rh f?rl fd 0 h fd 0 l read one word to fd0l/fd0h note: 1. writing a data into high byte, which means the h/l data is written into write buffer, will cause the flash memory address increased by one automatically and the new address will be loaded to the farh and farl registers. however, the user can also fll the new address by flling the data into farh and farl registers in the same page, then the data will be written into the corresponding address. 2. if the address already reached the boundary of the fash memory, such as 11111b of the 32 words or 111111b of the 64 words. at this moment, the address will not be increased and the address will stop at the last address of that page and the writing data is invalid. 3. at this point, the user has to set a new address again to fll a new data. 4. if the data is writing using the write buffer, the write buffer will be cleared by hardware automatically after the write procedure is ready in 2ms. 5. fisrt time use the write buffer or renew the data in the write buffer, the user can use to clear buffer bit (clwb) to clear write buffer.
rev. 1.00 ?6 ???i? 0?? ?01? rev. 1.00 ?7 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi isp bootloader the devices provide the isp bootloader function to upgrade the software in the flash memory. the user can select to use the isp bootloader application software provided by holtek ide tool or to create his own bootloader software. when the holtek bootloader software is selected, that will occupy 0.5k words area in the flash memory. the accompanyimg diagram illustrates the flash memory structure with holtek bootloader software. ht 66 fb 540 bank 1 last page ht 66 fb 550 ht 66 fb 5 60 0000 h 0 d 00 h 0 dffh last page bank 0 boot?oade? boot?oade? boot?oade? 000 h 1 d 00 h 1 dffh 0000 h 1 fffh last page ? d 00 h ? dffh flash memory structure with bootloader software flash program memory registers there are two address registers, four 16-bit data registers and one control register. the control register is located in bank1 and the other registers are located in bank 0. read and write operations to the flash memory are carried out in 16-bit data operations using the address and data registers and the control register. several registers control the overall operation of the internal flash program memory. the address registers are named farl and farh, the data registers are named fdnl and fdnh, and the single control register is named fcr. as the farl and fdnl registers are located in bank 0, they can be directly accessed in the same was as any other special function register. the farh, fdnh and fcr registers however, being located in bank1, cannot be addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register, iar1.
rev. 1.00 ?8 ???i? 0?? ?01? rev. 1.00 ?9 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi program memory register list ? HT66FB540 name bit 7 6 5 4 3 2 1 0 f ?rl d7 d6 d5 d4 d? d? d1 d0 f ?rh d11 d10 d9 d8 fd0l d7 d6 d5 d4 d? d? d1 d0 fd0h d15 d14 d1? d1? d11 d10 d9 d8 fd1l d7 d6 d5 d4 d? d? d1 d0 fd1h d15 d14 d1? d1? d11 d10 d9 d8 fd?l d7 d6 d5 d4 d? d? d1 d0 fd?h d15 d14 d1? d1? d11 d10 d9 d8 fd?l d7 d6 d5 d4 d? d? d1 d0 fd?h d15 d14 d1? d1? d11 d10 d9 d8 fcr cfwen fmod? fmod1 fmod0 bwt fwt fden frd frcr fswrst clwb ? ht66fb550 name bit 7 6 5 4 3 2 1 0 f ?rl d7 d6 d5 d4 d? d? d1 d0 f ?rh d1? d11 d10 d9 d8 fd0l d7 d6 d5 d4 d? d? d1 d0 fd0h d15 d14 d1? d1? d11 d10 d9 d8 fd1l d7 d6 d5 d4 d? d? d1 d0 fd1h d15 d14 d1? d1? d11 d10 d9 d8 fd?l d7 d6 d5 d4 d? d? d1 d0 fd?h d15 d14 d1? d1? d11 d10 d9 d8 fd?l d7 d6 d5 d4 d? d? d1 d0 fd?h d15 d14 d1? d1? d11 d10 d9 d8 fcr cfwen fmod? fmod1 fmod0 bwt fwt fden frd frcr fswrst clwb
rev. 1.00 ?8 ???i? 0?? ?01? rev. 1.00 ?9 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb560 name bit 7 6 5 4 3 2 1 0 f ?rl d7 d6 d5 d4 d? d? d1 d0 f ?rh d1? d1? d11 d10 d9 d8 fd0l d7 d6 d5 d4 d? d? d1 d0 fd0h d15 d14 d1? d1? d11 d10 d9 d8 fd1l d7 d6 d5 d4 d? d? d1 d0 fd1h d15 d14 d1? d1? d11 d10 d9 d8 fd?l d7 d6 d5 d4 d? d? d1 d0 fd?h d15 d14 d1? d1? d11 d10 d9 d8 fd?l d7 d6 d5 d4 d? d? d1 d0 fd?h d15 d14 d1? d1? d11 d10 d9 d8 fcr cfwen fmod? fmod1 fmod0 bwt fwt fden frd frcr fswrst clwb farl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown %lw a )odvk?urjudp0hprudgguhvv )odvk?urjudp0hprudgguhvvelwaelw farh register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name d11 d10 d9 d8 r/w r/w r/w r/w r/w por x x x x x unknown %lw a 5hvhuyhgfdqqrwehxvhg %lw a )odvk?urjudp0hprudgguhvv )odvk?urjudp0hprudgguhvvelw aelw ? ht66fb550 bit 7 6 5 4 3 2 1 0 name d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w por x x x x x x unknown %lw a 5hvhuyhgfdqqrwehxvhg %lw a )odvk?urjudp0hprudgguhvv )odvk?urjudp0hprudgguhvvelwaelw
rev. 1.00 40 ???i? 0?? ?01? rev. 1.00 41 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb560 bit 7 6 5 4 3 2 1 0 name d1? d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w por x x x x x x x unknown %lw a 5hvhuyhgfdqqrwehxvh %lw a )odvk?urjudp0hprudgguhvv )odvk?urjudp0hprudgguhvvelwaelw fcr register bit 7 6 5 4 3 2 1 0 name cfwen fmod? fmod1 fmod0 bwt fwt frden frd r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw cfwen: odvk520 :ulwh qdeohelw:1frqwuroelw lvdeoh 8qlpsohphqwhg 7klv elw lv xvhg wr frqwuro wkh :1 elw hqdeoh ru glvdeoh :khq wklv elw lv fohduhg wr orz e vriwzduh wkh odvk phpru zulwh hqdeoh frqwuro elw :1 zloo eh fohduhg wr orzdvzhoo ,wv lqhiihfwlyhwrvhwwklvelwwrkljk 7khxvhufdqfkhfnwklvelw wrfrqup wkh:1vwdwxv lw fmod2~fmod0: odvk3urjudp phprurqjxudwlrqrswlrqphprurshudwlqj prghfrqwuroelwv zulwhphpruprgh 3djhhudvhprgh 5hvhuyhg 5hdgphpruprgh 5hvhuyhg 5hvhuyhg :1odvkphpruzulwhhqdeohelwfrqwuroprgh 5hvhuyhg lw bwt: 0rghfkdqjhfrqwuro 0rghfkdqjhffohkdvqlvkhg fwlydwhdprghfkdqjhffoh 7klv elw zloo eh dxwrpdwlfdoo uhvhw wr hur e wkh kdugzduh diwhu wkh prgh fkdqjh ffohkdvqlvkhg lw fwt: odvkphpru :ulwh rqwuro :ulwh ffohkdvqlvkhg fwlydwhdzulwhffoh 7klv lv wkh odvk phpru :ulwh rqwuro lw dqg zkhq vhw kljk e wkh dssolfdwlrq surjudp zloo dfwlydwh d zulwh ffoh 7klv elw zloo eh dxwrpdwlfdoo uhvhw wr hur e wkh kdugzduhdiwhuwkhzulwhffohkdvqlvkhg lw frden: odvk0hpru5hdgqdeoh lvdeoh qdeoh 7klv lv wkh odvk phpru 5hdg qdeoh lw zklfk pxvw eh vhw kljk ehiruh odvk phpru uhdg rshudwlrqv duh fduulhg rxw ohdulqj wklv elw wr hur zloo lqklelw odvk phpruuhdgrshudwlrqv
rev. 1.00 40 ???i? 0?? ?01? rev. 1.00 41 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi bit 0 frd: flash memory read control 0: read cycle has fnished 1: activate a read cycle this is the flash memory read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no effect if the rden has not frst been set high. note: the fwt, frden and frd registers can not be set to "1" at the same time with a single instruction. frcr register bit 7 6 5 4 3 2 1 0 name fswrst clwb r/w r/w r/w por 0 0 bit 7~5 unimplemented bit 4 fswrst: control bit must be to 0 bit 3~1 unimplemented bit 0 clwb: flash program memory write buffer clear control bit 0: do not initiate clear write buffer or clear process 1: initiate clear write buffer process this bit is used to control the flash program memory clear write buffer process. it will be set by software and cleared by hardware. in application programming C iap offering users the convenience of flash memory multi-programming features, the ht66fb5x0 series of devices not only provide an isp function, but also an additional iap function. the convenience of the iap function is that it can execute the updated program procedure using its internal frmware, without requiring an external program writer or pc. in addition, the iap interface can also be any type of communication protocol, such as uart or usb, using i/o pins. designers can assign i/o pins to communicate with the external memory device, including the updated program. regarding the internal firmware, the user can select versions provided by holtek or create their own. the following section illustrates the procedures regarding how to implement iap frmware. enable flash write control procedure the first procedure to implement the iap firmware is to enable the flash write control which includes the following steps. ? write data 110 to the fmod [2:0] bits in the fcr register to enable the flash write control bit, fwen. ? set the bwt bit in the fcr register to 1. ? these devices will start a 300s counter. the user should write the correct data pattern into the flash data registers, namely fd1l~fd3l and fd1h~fd3h, during this period of time. ? once the 300s counter has overfowed or if the written pattern is incorrect, the enable flash write control procedure will be invalid and the user should repeat the above procedure. ? no matter whether the procedure is valid or not, the devices will clear the bwt bit automatically.
rev. 1.00 4? ???i? 0?? ?01? rev. 1.00 4? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? the enable flash write pattern data is (00h, 04h, 0dh, 09h, c3h, 40h) and it should be written into the flash data registers. ? once the flash write operation is enabled, the user can update the flash memory using the flash control registers. ? to disable the flash write procedure, the user can only clear the cfwen bit in the fcr register. there is no need to execute the above procedure. set fwen fmod 2 ~ 0 = 110 : set fwen bit bwt = 1 , hardware set a counter wrtie the following pattern to flash data register fd 1 l = 00 h , fd 1 h = 04 h fd 2 l = 0 dh , fd 2 h = 09 h fd 3 l = c 3 h , fd 3 h = 40 h is pattern is correct ? cfwen=0 set fwen bit fail no cfwen=1 set fwen bit success . yes end is counter overflow ? no yes bwt=0?
rev. 1.00 4? ???i? 0?? ?01? rev. 1.00 4? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi flash memory write and read procedures the following fow charts illustrate the write and read flash memory procedures. write flash rom set fwen procedure fwt= 1 flash address register: fah=xxh, fal=xxh write the following data to register: fd0 l=xxh, fd0 h =xxh yes page erase fah=xxh, fal=xxh fmod 2~0=001 fwt=1 fwt= 0 ? yes n o write fmod2 ~ 0 = 000 clear cfwen bit end write finish ? yes n o write data to write buffer [( rom 8k1 ~ 32 words data ) or (rom > 8k1 ~ 64 words data)]: write buffer finish? n o write next page write next data y es fwt= 0 ? n o write flash program rom procedure
rev. 1.00 44 ???i? 0?? ?01? rev. 1.00 45 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi read flash or option frden= 0 clear cfwen bit end read finish ? yes no fmod2 ~ 0 =011 frden=1 flash address register: fah=xxh, fal=xxh frd =0 ? yes no read value: fd0l=xxh, fd0 h =xxh frd =1 read flash program procedure
rev. 1.00 44 ???i? 0?? ?01? rev. 1.00 45 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi in circuit programming C icp the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in- circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re- insertion of the device. holtek writer pins mcu programming pins pin description icpd? udn p?og?amming se?ia? data icpck res p?og?amming c?ock vdd vdd/hvdd powe? su???y vss vss g?ound the program memory can be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply and one line for the reset. the technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. during the programming process, taking control of the udn and res pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins.
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?? note: * may be resistor or capacitor. the resistance of * must be greater than 300 w or the capacitance of * must be less than 1nf. on-chip debug support C ocds there is an ev chip named ht66vb540/ht66vb550/ht66vb560 which is used to emulate the HT66FB540/ht66fb550/ht66fb560 device. the ht66vb540/ht66vb550/ht66vb560 device also provides the on-chip debug function to debug the HT66FB540/ht66fb550/ht66fb560 device during development process. the two devices, HT66FB540/ht66fb550/ht66fb560 and ht66vb540/ht66vb550/ht66vb560, are almost functional compatible except the on-chip debug function. users can use the ht66vb540/ht66vb550/ht66vb560 device to emulate the HT66FB540/ht66fb550/ht66fb560 device behaviors by connecting the ocdsda and ocdsck
rev. 1.00 46 ???i? 0?? ?01? rev. 1.00 47 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi pins to the holtek ht-ide development tools. the ocdsda pin is the ocds data/address input/ output pin while the ocdsck pin is the ocds clock input pin. when users use the ht66vb540/ ht66vb550/ht66vb560 ev chip for debugging, the corresponding pin functions shared with the ocdsda and ocdsck pins in the HT66FB540/ht66fb550/ht66fb560 device will have no effect in the ht66vb540/ht66vb550/ht66vb560 ev chip. for more detailed ocds information, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip pins pin description ocdsd? ocdsd? on-chi? debug su??o?t data/?dd?ess in?ut/out?ut ocdsck ocdsck on-chi? debug su??o?t c?ock in?ut vdd vdd/hvdd powe? su???y gnd vss g?ound ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. here are located registers which are necessary for correct operation of the devices. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. device capacity banks HT66FB540 51?8 0: 80h~ffh 1: 80h~ffh ?: 80h~ffh ?: 80h~ffh ht66fb550 7688 0: 80h~ffh 1: 80h~ffh ?: 80h~ffh ?: 80h~ffh 4: 80h~ffh 5: 80h~ffh ht66fb560 10?48 0: 80h~ffh 1: 80h~ffh ?: 80h~ffh ?: 80h~ffh 4: 80h~ffh 5: 80h~ffh 6: 80h~ffh 7: 80h~ffh the second area of data memory is known as the general purpose data memory, which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into several banks, the structure of which depends upon these devices chosen. the special purpose data memory registers are accessible in all banks, with the exception of the , fcr, farh and fdnh registers at address from 40h to 46h, which are only accessible in bank 1. switching between the different data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for all devices is the address 00h.
rev. 1.00 46 ???i? 0?? ?01? rev. 1.00 47 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540 bank0~3 bank0, 2~3 bank1 00h i?r0 40h unused frcr 01h mp0 41h unused fcr 0?h i?r1 4?h f ?rl f ?rh 0?h mp1 4?h fd0l fd0h 04h bp 44h fd1l fd1h 05h ?cc 45h fd?l fd?h 06h pcl 46h fd?l fd?h 07h tblp 47h tmpc0 08h tblh 48h tmpc1 09h tbhp 49h tm0c0 0?h st ? tus 4?h tm0c1 0bh smod 4bh unused 0ch lvdc 4ch tm0dl 0dh integ 4dh tm0dh 0eh wdtc 4eh tm0?l 0fh tbc 4fh tm0?h 10h intc0 50h tm0rp 11h intc1 51h unused 1?h intc? 5?h tm1c0 1?h intc? 5?h tm1c1 14h mfi0 54h tm1dl 15h mfi1 55h tm1dh 16h mfi? 56h tm1?l 17h unused 57h tm1?h 18h p? wu 58h tm?c0 19h p ?pu 59h tm?c1 1?h p? 5?h tm?dl 1bh p? c 5bh tm?dh 1ch p ?dir 5ch tm??l 1dh p ?oi 5dh tm??h 1eh pslew 5eh tm?c0 1fh pxwu 5fh tm?c1 ?0h pxpu 60h tm?dl ?1h pxoi 61h tm?dh ??h pb 6?h tm??l ??h pbc 6?h tm??h ?4h unused 64h usb_st ? t ?5h unused 65h uint ?6h pd 66h usc ?7h pdc 67h usr ?8h pe 68h ucc ?9h pec 69h ? wr ??h unused 6?h stli ?bh unused 6bh stlo ?ch unused 6ch sies ?dh unused 6dh misc ?eh unused 6eh ufien ?fh ?drl 6fh ufoen ?0h ?drh 70h ufc0 ?1h ?dcr0 71h unused ??h ?dcr1 7?h fifo0 ??h ?cer0 7?h fifo1 ?4h unused 74h fifo? ?5h cp0c 75h fifo? ?6h cp1c 76h unused ?7h i? ctoc 77h unused ?8h simc0 78h unused ?9h simc1 79h unused ??h simd 7?h ctrl ?bh sim?/simc? 7bh lvrc ?ch spi?c0 7ch unused ?dh spi?c1 7dh p ?ps0 ?eh spi?d 7eh p ?ps1 ?fh sbsc 7fh sysc HT66FB540 special purpose data memory
rev. 1.00 48 ???i? 0?? ?01? rev. 1.00 49 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ht66fb550 bank0~5 bank0, 2~5 bank1 00h i?r0 40h unused frcr 01h mp0 41h unused fcr 0?h i?r1 4?h f ?rl f ?rh 0?h mp1 4?h fd0l fd0h 04h bp 44h fd1l fd1h 05h ?cc 45h fd?l fd?h 06h pcl 46h fd?l fd?h 07h tblp 47h tmpc0 08h tblh 48h tmpc1 09h tbhp 49h tm0c0 0?h st ? tus 4?h tm0c1 0bh smod 4bh unused 0ch lvdc 4ch tm0dl 0dh integ 4dh tm0dh 0eh wdtc 4eh tm0?l 0fh tbc 4fh tm0?h 10h intc0 50h tm0rp 11h intc1 51h unused 1?h intc? 5?h tm1c0 1?h intc? 5?h tm1c1 14h mfi0 54h tm1dl 15h mfi1 55h tm1dh 16h mfi? 56h tm1?l 17h unused 57h tm1?h 18h p? wu 58h tm?c0 19h p ?pu 59h tm?c1 1?h p? 5?h tm?dl 1bh p? c 5bh tm?dh 1ch p ?dir 5ch tm??l 1dh p ?oi 5dh tm??h 1eh pslew 5eh tm?c0 1fh pxwu 5fh tm?c1 ?0h pxpu 60h tm?dl ?1h pxoi 61h tm?dh ??h pb 6?h tm??l ??h pbc 6?h tm??h ?4h pc 64h usb_st ? t ?5h pcc 65h uint ?6h pd 66h usc ?7h pdc 67h usr ?8h pe 68h ucc ?9h pec 69h ? wr ??h unused 6?h stli ?bh unused 6bh stlo ?ch unused 6ch sies ?dh unused 6dh misc ?eh unused 6eh ufien ?fh ?drl 6fh ufoen ?0h ?drh 70h ufc0 ?1h ?dcr0 71h ufc1 ??h ?dcr1 7?h fifo0 ??h ?cer0 7?h fifo1 ?4h ?cer1 74h fifo? ?5h cp0c 75h fifo? ?6h cp1c 76h fifo4 ?7h i? ctoc 77h fifo5 ?8h simc0 78h unused ?9h simc1 79h unused ??h simd 7?h ctrl ?bh sim?/simc? 7bh lvrc ?ch spi?c0 7ch unused ?dh spi?c1 7dh p ?ps0 ?eh spi?d 7eh p ?ps1 ?fh sbsc 7fh sysc ht66fb550 special purpose data memory
rev. 1.00 48 ???i? 0?? ?01? rev. 1.00 49 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ht66fb560 bank0~7 bank0, 2~7 bank1 00h i?r0 40h unused frcr 01h mp0 41h unused fcr 0?h i?r1 4?h f ?rl f ?rh 0?h mp1 4?h fd0l fd0h 04h bp 44h fd1l fd1h 05h ?cc 45h fd?l fd?h 06h pcl 46h fd?l fd?h 07h tblp 47h tmpc0 08h tblh 48h tmpc1 09h tbhp 49h tm0c0 0?h st ? tus 4?h tm0c1 0bh smod 4bh unused 0ch lvdc 4ch tm0dl 0dh integ 4dh tm0dh 0eh wdtc 4eh tm0?l 0fh tbc 4fh tm0?h 10h intc0 50h tm0rp 11h intc1 51h unused 1?h intc? 5?h tm1c0 1?h intc? 5?h tm1c1 14h mfi0 54h tm1dl 15h mfi1 55h tm1dh 16h mfi? 56h tm1?l 17h unused 57h tm1?h 18h p? wu 58h tm?c0 19h p ?pu 59h tm?c1 1?h p? 5?h tm?dl 1bh p? c 5bh tm?dh 1ch p ?dir 5ch tm??l 1dh p ?oi 5dh tm??h 1eh pslew 5eh tm?c0 1fh pxwu 5fh tm?c1 ?0h pxpu 60h tm?dl ?1h pxoi 61h tm?dh ??h pb 6?h tm??l ??h pbc 6?h tm??h ?4h pc 64h usb_st ? t ?5h pcc 65h uint ?6h pd 66h usc ?7h pdc 67h usr ?8h pe 68h ucc ?9h pec 69h ? wr ??h pf 6?h stli ?bh pfc 6bh stlo ?ch pfpu 6ch sies ?dh pfwkup 6dh misc ?eh unused 6eh ufien ?fh ?drl 6fh ufoen ?0h ?drh 70h ufc0 ?1h ?dcr0 71h ufc1 ??h ?dcr1 7?h fifo0 ??h ?cer0 7?h fifo1 ?4h ?cer1 74h fifo? ?5h cp0c 75h fifo? ?6h cp1c 76h fifo4 ?7h i? ctoc 77h fifo5 ?8h simc0 78h fifo6 ?9h simc1 79h fifo7 ??h simd 7?h ctrl ?bh sim?/simc? 7bh lvrc ?ch spi?c0 7ch unused ?dh spi?c1 7dh p ?ps0 ?eh spi?d 7eh p ?ps1 ?fh sbsc 7fh sysc ht66fb560 special purpose data memory
rev. 1.00 50 ???i? 0?? ?01? rev. 1.00 51 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi special function register description most of the special function register details will be described in the relevant functional section; however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register. direct addressing can only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with frst ram address mov mp0,a ; setup memory pointer with frst ram address loop: clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specifc ram addresses.
rev. 1.00 50 ???i? 0?? ?01? rev. 1.00 51 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi bank pointer C bp depending upon which devices are used, the program and data memory are divided into several banks. selecting the required program and data memory area is achieved using the bank pointer. bit 5 of the bank pointer is used to select program memory bank 0 or 1, while bits 0~2 are used to select data memory banks 0~6. the data memory is initialised to bank 0 after a reset, except for a wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. it should be noted that the special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within any bank. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accessing data from banks other than bank 0 must be implemented using indirect addressing. as both the program memory and data memory share the same bank pointer register, care must be taken during programming. device bit 7 6 5 4 3 2 1 0 HT66FB540 dmbp1 dmbp0 ht66fb550 dmbp? dmbp1 dmbp0 ht66fb560 pmbp0 dmbp? dmbp1 dmbp0 bp registers list bp register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name dmbp1 dmbp0 r/w r/w r/w por 0 0 bit 7~3 unimplemented bit 1~0 dmbp1, dmbp0: select data memory banks 00: bank 0 01: bank 1 10: bank 2 11: bank 3 ? ht66fb550 bit 7 6 5 4 3 2 1 0 name dmbp? dmbp1 dmbp0 r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented bit 1~0 dmbp2, dmbp1, dmbp0: select data memory banks 000: bank 0 001: bank 1 010: bank 2 011: bank 3 100: bank 4 101: bank 5 110~111: undefned
rev. 1.00 5? ???i? 0?? ?01? rev. 1.00 5? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb560 bit 7 6 5 4 3 2 1 0 name pmbp0 dmbp? dmbp1 dmbp0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented bit 5 pmbp0: select program memory banks 0: bank 0, program memory address is from 0000h~1fffh 1: bank 1, program memory address is from 2000h~3fffh bit 4~3 unimplemented bit 2~0 dmbp2~dmbp0: select data memory banks 000: bank 0 001: bank 1 010: bank 2 011: bank 3 100: bank 4 101: bank 5 110: bank 6 111: bank 7 accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointer and indicates the location where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.00 5? ???i? 0?? ?01? rev. 1.00 5? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (to). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf fag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the "clr wdt" or "halt" instruction. the pdf fag is affected only by executing the "halt" or "clr wdt" instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ?c c r/w r r r/w r/w r/w r/w por 0 0 x x x x " x" unknown bit 7, 6 unimplemented, read as 0 bit 5 to: watchdog time-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf: power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov: overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z: zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero
rev. 1.00 54 ???i? 0?? ?01? rev. 1.00 55 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi bit 1 ac: auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c: carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog timer and time base interrupts. external oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. all oscillator options are selected through the configuration options. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capability of dynamically switching between fast and slow system clock, these devices have the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name frequency pins exte?na? c?ysta? hxt 6mhz o? 1?mhz osc1/osc? inte?na? high s?eed rc hirc 1?mhz exte?na? low s?eed c?ysta? lxt ??.768khz xt1/xt? inte?na? low s?eed rc lirc ??khz oscillator types note: fo? usb a???ications? hxt must be connected a 6mhz o? 1?mhz c?ysta?. system clock confgurations there are several oscillator sources, two high speed oscillators and two low speed oscillators. the high speed system clocks are sourced from the external crystal/ceramic oscillator, the pll frequency generator and the internal 12mhz rc oscillator. the two low speed oscillators are the internal 32khz rc oscillator and the external 32.768khz crystal oscillator. selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2~cks0 bits in the smod register and as the system clock can be dynamically selected. the actual source clock used for each of the high speed and low speed oscillators is chosen via confguration options. the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2~cks0 bits in the smod register. note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. in addition, the internal pll frequency generator, whose clock source is supplied by an external crystal oscillator, can be enabled by a software control bit to generate various frequencies for the usb interface and system clock.
rev. 1.00 54 ???i? 0?? ?01? rev. 1.00 55 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi hxt o sc ? config . o?tion se?ects 6 o? 1? mh z xt?l high s?eed osci??ato? 6 mh z sysclk bit pll pll bit 48 mhz usbcken bit t o usbck ci?cuits 16 mhz 1? mhz 6 mhz sysclk bit h osc configu?ation o?tion h osc pll bit f sys 16 mhz bit f h p?esca?e? f h / ? f h / 4 f h / 8 f h / 16 f h / ?? f h / 64 f sys f h f l wdt hclk bit cks 0 - cks ? bit h irc o sc usbcken bit configu?ation o?tion lirc o sc low s?eed osci??ato? lxt o sc fast w ake - u? f?om sleep o? idle mode cont?o? ( fo? hxt on?y ) f l time base pll c?ock h osc f s ub f tb system clock confgurations external crystal oscillator C hxt the external crystal system oscillator is one of the high frequency oscillator.
? ? ?? crystal oscillator C hxt crystal oscillator c1 and c2 values crystal frequency c1 c2 16mhz 0?f 0?f 1?mhz 0?f 0?f 8mhz 0?f 0?f 6mhz 0?f 0?f 4mhz 0?f 0?f 1mhz 100?f 100?f note: 1. c1 and c? va?ues a?e fo? guidance on? y. crystal recommended capacitor values note: fo? usb a???ications? hxt must be connected a 6mhz o? 1?mhz c?ysta?.
rev. 1.00 56 ???i? 0?? ?01? rev. 1.00 57 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi internal pll frequency generator the internal pll frequency generator is used to generate the frequency for the usb interface and the system clock. this pll generator can be enabled or disabled by the pll control bit in the usc register. after a power on reset, the pll control bit will be set to 0 to turn on the pll generator. the pll generator will provide the fxed 48mhz frequency for the usb operating frequency and another frequency for the system clock source which can be either 6mhz, 12mhz or 16mhz. the selection of this system frequency is implemented using the sysclk, fsys16mhz and usbcken bits in the ucc register. in addition, the system clock can be selected as the hxt via these control bits. the clk_adj bit is used to adjust the pll clock automatically. sysc register bit 7 6 5 4 3 2 1 0 name clk_?dj usbdis rubus hfv r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 clk_adj: pll clock automatic adjustment function 0: disable 1: enable note that if the user selects the hirc as the system clock, the clk_adj bit must be set to 1 to adjust the pll frequency automatically. bit 6 usbdis: usb sie control bit usb related control bit, described elsewhere bit 5 rubus: ubus pin pull low resistor usb related control bit, described elsewhere bit 4~3 "": unimpleme nted, read as "0" bit 2 hfv : non-usb mode high frequency voltage control 0: for usb mode - bit must be cleared to zero. 1: for non-usb mode - bit must be set high. ensures that the higher frequency can work at lower voltages. a higher frequency is >8mhz and is used for the system clock f . bit 1~0 "": unimpleme nted, read as "0"
rev. 1.00 56 ???i? 0?? ?01? rev. 1.00 57 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ucc register bit 7 6 5 4 3 2 1 0 name rct?? sysclk fsys16mhz susp? usbcken eps1 eps0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 rctrl: 7.5k resistor between udp and ubus control bit usb related control bit, described elsewhere bit 6 sysclk: system clock frequency select bit 0: 12mhz 1: 6mhz note: if a 6mhz crystal or resonator is used for the mcu, this bit should be set to 1. if a 12mhz crystal or resonator is used, then this bit should be set to 0. if the 12mhz hirc is selected, then this bit must be set to 0. bit 5 fsys16mhz: pll 16mhz output control bit 0: hxt 1: pll 16mhz bit 4 susp2: reduce power consumption in suspend mode control bit usb related control bit, described elsewhere bit 3 usbcken: usb clock control bit 0: disable 1: enable bit 2 unimplemented bit 1~0 eps1, eps0: accessing endpoint fifo selection usb related control bit, described elsewhere usc register bit 7 6 5 4 3 2 1 0 name urd selps? pll selusb resume urst rmwk susp r/w r/w r/w r/w r/w r r/w r/w r por 1 0 0 0 0 0 0 0 bit 7 urd: usb reset signal control function defnition usb related control bit, described elsewhere bit 6 selps2: the chip works under ps2 mode indicator bit usb related control bit, described elsewhere bit 5 pll: pll control bit 0: turn-on pll 1: turn-off pll bit 4 selusb: the chip works under usb mode indicator bit usb related control bit, described elsewhere bit 3 resume: usb resume indication bit usb related control bit, described elsewhere bit 2 urst: usb reset indication bit usb related control bit, described elsewhere bit 1 rmwk: usb remote wake-up command usb related control bit, described elsewhere bit 0 susp: usb suspend indication usb related control bit, described elsewhere
rev. 1.00 58 ???i? 0?? ?01? rev. 1.00 59 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi the following table illustrates the pll output frequency selected by the related control bits. high frequency system clock f h selection table: pll usbcken fsys16mhz f h 0 0 0 hosc (hxt o ? hirc) 0 0 1 f pll C 16mhz 0 1 0 f pll C 6mhz o? 1? mhz? de?ending on the sysclk bit in the ucc ?egiste? se?ection 0 1 1 f pll C 16mhz 1 x x hosc (hxt o ? hirc) x: stand fo? dont ca?e internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a fixed frequency of 12mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3.3v or 5v and at a temperature of 25?c degrees, the fxed oscillation frequency of 12mhz will have a tolerance within 3% (non-usb mode). note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pd0 and pd1 are free for use as normal i/o pins. the hirc has its own power supply pin, hvdd. the hvdd pin must be connected to vdd and an 0.1 m f capacitor to ground. external 32.768khz crystal oscillator C lxt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. this clock source has a fxed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins xt1 and xt2. the external resistor and capacitor components connected to the 32.768khz crystal are necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. during power-up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microcontroller enters the sleep or idle mode, the system clock is switched off to stop microcontroller activity and to conserve power. however, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. to do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specification. the external parallel feedback resistor, rp, is required. some confguration options determine if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins. ? if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o pins. ? if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the xt1/xt2 pins.
rev. 1.00 58 ???i? 0?? ?01? rev. 1.00 59 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi
? ? ? ?? ?- ? ? ? external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 ??.768khz 10?f 10?f note: 1. c1 and c? va?ues a?e fo? guidance on? y. ?. r p =5m~10m is ?ecommended. 32.768khz crystal recommended capacitor values lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the tbc register. lxtlp bit lxt mode 0 quick sta?t 1 low-?owe? after power on the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. however, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will always function normally, the only difference is that it will take more time to start up if in the low-power mode. internal 32khz oscillator C lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25?c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%.
rev. 1.00 60 ???i? 0?? ?01? rev. 1.00 61 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi supplementary internal clocks the low speed oscillators, in addition to providing a system clock source are also used to provide a clock source to two other devices functions. these are the watchdog timer and the time base interrupts. operating modes and system clocks present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conficting requirements that are especially true in battery powered portable applications. the fast clocks required for high performance will by their nature increase current consumption and of course vice versa, lower speed clocks reduce current consumption. as holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the devices have many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using confguration options and register programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency, f h , or low frequency, f l , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from either a hxt, pll frequency generator or hirc oscillator, selected via a confguration option. the low speed system clock source can be sourced from internal clock f l . if f l is selected then it can be sourced by either the lxt or lirc oscillators, selected via a confguration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there are two additional internal clocks for the peripheral circuits, the substitute clock, f sub , and the time base clock, f tbc . each of these internal clocks is sourced by either the lxt or lirc oscillators, selected via confguration options. the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times.
rev. 1.00 60 ???i? 0?? ?01? rev. 1.00 61 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi hxt o sc ? config . o?tion se?ects 6 o? 1? mh z xt?l high s?eed osci??ato? 6 mh z sysclk bit pll pll bit 48 mhz usbcken bit t o usbck ci?cuits 16 mhz 1? mhz 6 mhz sysclk bit h osc configu?ation o?tion h osc pll bit f sys 16 mhz bit f h p?esca?e? f h / ? f h / 4 f h / 8 f h / 16 f h / ?? f h / 64 f sys f h f l wdt hclk bit cks 0 - cks ? bit h irc o sc usbcken bit configu?ation o?tion lirc o sc low s?eed osci??ato? lxt o sc fast w ake - u? f?om sleep o? idle mode cont?o? ( fo? hxt on?y ) f l time base pll c?ock h osc f s ub f tb system clock confgurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. the f sub clock is used as one of the clock sources for the watchdog timer. the f tbc clock is used as a source for the time base interrupt functions and for the tms. system operation modes there are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. there are two modes allowing normal operation of the microcontroller, the normal mode and slow mode. the remaining four modes, the sleep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operation mode description cpu f sys f sub f tbc norm? l mode on f h ~f h /64 on on slow mode on f l on on idle0 mode off off on on idle1 mode off on on on sleep0 mode off off off off sleep1 mode off off on off
rev. 1.00 6? ???i? 0?? ?01? rev. 1.00 6? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the pll frequency generator, hxtor hirc oscillators. the high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. ? slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. ? sleep0 mode the sleep0 mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep0 mode the cpu will be stopped, and the f sub clock will be stopped too, and the watchdog timer function is disabled. in this mode, the lvden is must set to "0". if the lvden is set to "1", it wont enter the sleep0 mode. ? sleep1 mode the sleep1 mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep1 mode the cpu will be stopped. however, the f sub clock will continue to operate if the lvden is "1" or the watchdog timer function is enabled. ? idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is low. in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watchdog timer, tms and sim. in the idle0 mode, the system oscillator will be stopped. in the idle0 mode the watchdog timer clock, f sub , will be on. ? idle1 mode the idle1 mode is entered when an halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the watchdog timer, tms and sim. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode the watchdog timer clock, f sub , will be on.
rev. 1.00 6? ???i? 0?? ?01? rev. 1.00 6? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi control register a single register, smod, is used for overall control of the internal clocks within these devices. smod register bit 7 6 5 4 3 2 1 0 name cks? cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 cks2~cks0: the system clock selection when hlclk is 0 000: f l (f lxt or f lirc 001: f l (f lxt or f lirc 010: f 011: f /32 100: f 101: f /8 110: f 111: f /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fsten: fast wake-up control (only for hxt) 0: disable 1: enable this is the fast wake-up control bit which determines if the f clock source is initially used after these devices wakes up. when the bit is high, the f clock source can be used as a temporary system clock to provide a faster wake up time as the f clock is available. bit 3 lto: low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscillator ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the lxt oscillator is used and 1~2 clock cycles if the lirc oscillator is used. bit 2 hto: high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. this fag is cleared to 0 by hardware when these devices are powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as 1 by the application program after devices power-on. the fag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the hxt oscillator is used and after 1024 clock cycles if the hirc oscillator is used. bit 1 idlen: idle mode control 0: disable 1: enable
rev. 1.00 64 ???i? 0?? ?01? rev. 1.00 65 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed these devices will enter the idle mode. in the idle1 mode the cpu will stop running but the system clock will continue to keep the peripheral functions operational, if fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low these devices will enter the sleep mode when a halt instruction is executed. bit 0 hlclk: system clock selection 0: f h /2~f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power. to minimise power consumption these devices can enter the sleep or idle0 mode, where the system clock source to these devices will be stopped. however when these devices are woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. to ensure the device is up and running as fast as possible a fast wake-up function is provided, which allows f sub , namely either the lxt or lirc oscillator, to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast wake-up function is f sub , the fast wake-up function is only available in the sleep1 and idle0 modes. when these devices are woken up from the sleep0 mode, the fast wake-up function has no effect because the f sub clock is stopped. the fast wake-up enable/disable function is controlled using the fsten bit in the smod register. if the hxt oscillator is selected as the normal mode system clock, and if the fast wake-up function is enabled, then it will take one to two t sub clock cycles of the lirc or lxt oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 hxt clock cycles have elapsed, at which point the hto fag will switch high and the system will switch over to operating from the hxt oscillator. if the hirc oscillator or lirc oscillator is used as the system oscillator then it will take 1024 clock cycles of the hirc or 1~2 cycles of the lirc to wake up the system from the sleep or idle0 mode. the fast wake-up bit, fsten will have no effect in these cases. hxt 0 10? 4 hxt cyc?es 10? 4 hxt cyc?es 1~? hxt cyc?es 1 10? 4 hxt cyc?es 1~? f sub cyc?es (system ?uns with f sub frst fo? 10? 4 hxt cyc?es and then switches ove? to ? un with the hxt c?ock) 1~? hxt cyc?es hirc x 10?4 hirc cyc?es 10?4 hirc cyc?es 1~? hirc cyc?es lirc x 1~? lirc cyc?es 1~? lirc cyc?es 1~? lirc cyc?es lxt x 10? 4 ltx cyc?es 10? 4 lxt cyc?es 1~? lxt cyc?es wake-u? times note that if the watchdog timer is disabled, which means that the lxt and lirc are all both off, then there will be no fast wake-up function available when these devices wake-up from the sleep0 mode.
rev. 1.00 64 ???i? 0?? ?01? rev. 1.00 65 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi

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? operating mode switching and wake-up these devices can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is executed, whether these devices enter the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h, to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the tms and the sim. the accompanying fowchart shows what happens when these devices move between the various operating modes. normal mode to slow mode switching when running in the normal mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to 0 and set the cks2~cks0 bits to 000 or 001 in the smod register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lxt or the lirc oscillators and therefore requires these oscillators to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register .
rev. 1.00 66 ???i? 0?? ?01? rev. 1.00 67 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi
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rev. 1.00 66 ???i? 0?? ?01? rev. 1.00 67 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi slow mode to normal mode switching in slow mode the system uses either the lxt or lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to 1 or hlclk bit is 0, but cks2~cks0 is set to 010, 011, 100, 101, 110 or 111. as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. entering the sleep0 mode there is only one way for these devices to enter the sleep0 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 0 and the wdt and lvd both off. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and time base clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped no matter if the wdt clock source originates from the f sub clock or from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the sleep1 mode there is only one way for these devices to enter the sleep1 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 0 and the wdt or lvd on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and time base clock will be stopped and the application program will stop at the halt instruction, but the wdt or lvd will remain with the clock source coming from the f sub clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock as the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared.
rev. 1.00 68 ???i? 0?? ?01? rev. 1.00 69 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi entering the idle0 mode there is only one way for these devices to enter the idle0 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in ctrl register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruction, but the time base clock and f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock and the wdt is enabled. the wdt will stop if its clock source originates from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the idle1 mode there is only one way for these devices to enter the idle1 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in ctrl register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and time base clock and f sub clock will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled regardless of the wdt clock source which originates from the f sub clock or from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of these devices to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on these devices. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonded pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps.
rev. 1.00 68 ???i? 0?? ?01? rev. 1.00 69 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external or usb reset ? an external rising or falling edge on port ? a system interrupt ? a wdt overfow if the system is woken up by an external or usb reset, these devices will experience a full system reset, however, if these devices are woken up by a wdt overfow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf fags. the pdf fag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port can be setup using the pawu or pxwu register to permit a negative transition on the pin to wake-up the system. when a pin wake-up occurs, the program will resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the halt instruction. in this situation, the interrupt which woke-up these devices will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. programming considerations the hxt and lxt oscillators both use the same sst counter. for example, if the system is woken up from the sleep0 mode and both the hxt and lxt oscillators need to start-up from an off state. the lxt oscillator uses the sst counter after hxt oscillator has fnished its sst period. ? if these devices are woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. these devices will execute frst instruction after hto is 1. at this time, the lxt oscillator may not be stability if f sub is from lxt oscillator. the same situation occurs in the power-on state. the lxt oscillator is not ready yet when the frst instruction is executed. ? if these devices are woken up from the sleep1 mode to normal mode, and the system clock source is from hxt oscillator and fsten is 1, the system clock can be switched to the lxt or lirc oscillator after wake up. ? there are peripheral functions, such as wdt, tms and sim, for which the f sys is used. if the system clock source is switched from f h to f l , the clock source to the peripheral functions mentioned above will change accordingly. ? the on/off condition of f sub depends upon whether the wdt is enabled or disabled as the wdt clock source is selected from f sub .
rev. 1.00 70 ???i? 0?? ?01? rev. 1.00 71 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the internal clock, f sub , which can be sourced from either the lxt or lirc oscillators, chosen via a confguration option. the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. the wdt function is allowed to enable or disable by setting the wdtc register data. watchdog timer control register a single register, wdtc, controls the required timeout period as well as the enable/disable operation. the wrf software reset fag will be indicated in the ctrl register. wdtc register bit 7 6 5 4 3 2 1 0 name we4 we? we? we1 we0 ws? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 wdt function software control 10101: wdt disabled 01010: wdt enabled other values: reset mcu when these bits are changed to any other values due to environmental noise the microcontroller will be reset; this reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the ctrl register will be set to 1 to indicate the reset source. bit 2~0 : wdt time-out period selection 000: 2 8 /f sub 001: 2 10 /f sub 010: 2 12 /f sub 011: 2 14 /f sub 100: 2 15 /f sub 101: 2 16 /f sub 110: 2 17 /f sub 111: 2 18 /f sub these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the timeout period.
rev. 1.00 70 ???i? 0?? ?01? rev. 1.00 71 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 bit 7 fsyson: f control in idle mode described elsewhere. bit 6~3 unimplemented, read as 0 bit 2 lvrf: lvr function reset fag described elsewhere. bit 1 lrf: lvr control register software reset fag described elsewhere. bit 0 wrf: wdt control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program. watchdog timer operation the watchdog timer operates by providing a device reset when its timer overfows. this means that in the application program and during normal operation the user has to strategically clear the watchdog timer before it overfows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instructions. if the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overfow and reset these devices. with regard to the watchdog timer enable/disable function, there are also fve bits, we4~we0, in the wdtc register to offer additional enable/disable and reset control of the watchdog timer.
rev. 1.00 7? ???i? 0?? ?01? rev. 1.00 7? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi wdt enable/disabled using the wdt control register the wdt is enabled/disabled using the wdt control register, the we4~we0 values can determine which mode the wdt operates in. the wdt will be disabled when the we4~we0 bits are set to a value of 10101b. the wdt function will be enabled if the we4~we0 bit value is equal to 01010b. if the we4~we0 bits are set to any other values other than 01010b and 10101b, it will reset these devices after 2~3 lirc clock cycles. after power on these bits will have the value of 01010b. wdt we4~we0 bits wdt function cont?o?? ed by wdt cont?o? registe? 10101b disab?e 01010b enab?e ?ny othe? va?ue reset mcu watchdog timer enable/disable control under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the watchdog timer contents. the frst is a wdt reset, which means a value other than 01010b or 10101b is written into the we4~we0 bit locations, the second is to use the watchdog timer software clear instructions and the third is via a halt instruction. there is only one method of using software instruction to clear the watchdog timer and that is to use the single clr wdt instruction to clear the wdt. the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration.

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rev. 1.00 7? ???i? 0?? ?01? rev. 1.00 7? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that these devices can be set to some predetermined condition irrespective of outside parameters. a hardware reset will of course be automatically implemented after these devices are powered-on, however there are a number of other hardware and software reset sources that can be implemented dynamically when these devices are running. reset overview the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defned state and ready to execute the frst program instruction. after this power-on reset, certain important internal registers will be set to defned states before the program instructions commence execution. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. these devices provide several reset sources to generate the internal reset signal, providing extended mcu protection. the different types of resets are listed in the accompanying table. no. reset name abbreviation indication bit register notes 1 powe?-on reset por ?uto gene?ated at ?owe? on ? reset pin res ha?dwa?e reset ? low-vo ?tage reset lvr lrf ctrl low v dd vo?tage 4 watchdog reset wdt to st ? tus 5 wdtc registe? setting softwa?e reset wrf ctrl w ?ite to wdtc ?egiste? reset source summary in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is forcefully pulled low. in such a case, known as a normal operation reset, some of the registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold.
rev. 1.00 74 ???i? 0?? ?01? rev. 1.00 75 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi reset functions there are several ways in which a microcontroller reset can occur, through events occurring both internally and externally: ? power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. power-on reset timing chart note: t rstd is power-on delay, typical time=50ms ? res pin although the microcontroller has an internal rc reset function, if the v dd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the fgures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environments where power line noise is signifcant. extern res circuit
rev. 1.00 74 ???i? 0?? ?01? rev. 1.00 75 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi more information regarding external reset circuits is located in application note ha0075e on the holtek website. pulling the res pin low using external hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. res reset timing chart note: t rstd is power-on delay, typical time=16.7ms ? low voltage reset C lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the devices and provide an mcu reset should the value fall below a certain predefned level. the lvr function is always enabled with a specific lvr voltage v lvr . if the supply voltage of the devices drops to within a range of 0.9v~v lvr such as might occur when changing the battery in battery powered applications, the lvr will automatically reset the devices internally and the lvrf bit in the ctrl register will also be set to 1. for a valid lvr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specifed by t lvr in the a.c. characteristics. if the low supply voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be selected by the lvs bits in the lvrc register. if the lvs7~lvs0 bits are changed to some different values by environmental noise, the lvr will reset the devices after 2~3 lirc clock cycles. when this happens, the lrf bit in the ctrl register will be set to 1. after power on the register will have the value of 01010101b. note that the lvr function will be automatically disabled when the devices enters the power down mode. low voltage reset timing chart note: t rstd is power-on delay, typical time=16.7ms
rev. 1.00 76 ???i? 0?? ?01? rev. 1.00 77 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi lvrc register bit 7 6 5 4 3 2 1 0 name lvs7 lvs6 lvs5 lvs4 lvs ? lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 lvs7~lvs0: lvr voltage select control 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v any other value: generates mcu reset C register is reset to por value when an actual low voltage condition occurs, as specifed by one of the four defned lvr voltage values above, an mcu reset will be generated. the reset operation will be activated after 2~3 lirc clock cycles. in this situation the register contents will remain the same after such a reset occurs. any register value, other than the four defned lvr values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 lirc clock cycles. however in this situation the register contents will be reset to the por value. ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 bit 7 fsyson: f control in idle mode describe elsewhere. bit 6~3 unimplemented, read as 0 bit 2 lvrf: lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low voltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf: lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the lvrc register contains any non defned lvr voltage register values. this in effect acts like a software reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf: wdt control register software reset fag describe elsewhere.
rev. 1.00 76 ???i? 0?? ?01? rev. 1.00 77 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a hardware res pin reset except that the watchdog time-out fag to will be set to 1. wdt time-out reset during normal operation timing chart note: t rstd is power-on delay, typical time=16.7ms ? watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the to fag will be set to 1. refer to the a.c. characteristics for t sst details. wdt time-out reset during sleep or idle timing chart note: the t sst is 15~16 clock cycles if the system clock source is provided by hirc. the t sst is 1024 clock for hxt or lxt. the t sst is 1~2 clock for lirc. wdtc register software reset a wdtc software reset will be generated when a value other than 10101 or 01010, exist in the highest fve bits of the wdtc register. the wrf bit in the ctrl register will be set high when this occurs, thus indicating the generation of a wdtc software reset. wdtc register bit 7 6 5 4 3 2 1 0 name we4 we? we? we1 we0 ws? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 we4, we3, we2, we1, we0: wdt software control 10101: wdt disable 01010: wdt enable (default) other: mcu reset bit 2~0 ws2, ws1, ws0 : wdt time-out period selection described elsewhere
rev. 1.00 78 ???i? 0?? ?01? rev. 1.00 79 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 powe?-on ?eset u u res ? lvr o? usb ?eset du? ing norm? l o? slow mode o?e?ation 1 u wdt time-out ?eset du?ing norm? l o? slow mode o?e?ation 1 1 wdt time-out ?eset du?ing idle o? sleep mode o?e?ation u stands fo? unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p?og?am counte? reset to ze?o inte??u?ts ??? inte??u?ts wi?? be disab?ed wdt c?ea? afte? ?eset? wdt begins counting time ?/event counte? time ? counte? wi?? be tu? ned off in?ut/out?ut po?ts i/o ?o?ts wi?? be setu? as in?uts? and ?n0~?nn is as ?/d in?ut ?in. stack pointe? stack pointe? wi?? ?oint to the to? of the stack the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type.
rev. 1.00 78 ???i? 0?? ?01? rev. 1.00 79 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi the HT66FB540 register states are summarized below: register reset (power on) wdt time-out/ wdtc software reset (normal operation) res reset/ lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) mp0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx mp1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ?cc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tbhp ---- xxxx ---- uuuu ---- uuuu ---- uuuu ---- uuuu ---- uuuu ---- uuuu st ? tus --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu --uu uuuu --uu uuuu bp ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 smod 0000 0011 0000 0011 0000 0011 0000 0011 uuuu uuuu 0000 0011 0000 0011 integ 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 lvdc --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu --00 -000 --00 -000 intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 intc1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 intc? 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 intc? -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu -000 -000 -000 -000 mfi0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 mfi1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 mfi? -0-0 -0-0 -0-0 -0-0 -0-0 -0-0 -0-0 -0-0 -u-u -u-u -0-0 -0-0 -0-0 -0-0 p? 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 p? c 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pb -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu -111 1111 -111 1111 pbc -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu -111 1111 -111 1111 pd --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu --11 1111 --11 1111 pdc --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu --11 1111 --11 1111 pe ---1 1101 ---1 1101 ---1 1101 ---1 1101 ---u uuuu ---1 1101 ---1 1101 pec ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---u uuuu ---1 1111 ---1 1111 ?drl (?drfs=0) xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- xxxx ---- xxxx ---- ?drl (?drfs=1) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ?drh (?drfs=0) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ?drh (?drfs=1) ---- xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- xxxx ---- xxxx ?dcr0 0110 -000 0110 -000 0110 -000 0110 -000 uuuu -uuu 0110 -000 0110 -000 ?dcr1 00-0 -000 00-0 -000 00-0 -000 00-0 -000 uu-u -uuu 00-0 -000 00-0 -000 ?cer0 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 wdtc 0101 0011 0101 0011 0101 0011 0101 0011 uuuu uuuu 0101 0011 0101 0011 tbc 0011 0111 0011 0111 0011 0111 0011 0111 uuuu uuuu 0011 0111 0011 0111 frcr ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u ---0 ---0 ---0 ---0 fcr 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 f ?rl xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx f ?rh ---- xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- xxxx ---- xxxx fd0l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd0h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx
rev. 1.00 80 ???i? 0?? ?01? rev. 1.00 81 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi register reset (power on) wdt time-out/ wdtc software reset (normal operation) res reset/ lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) fd1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd?l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd?h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd?l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd?h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx i? ctoc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 simc0 1110 000- 1110 000- 1110 000- 1110 000- uuuu uuu- 1110 000- 1110 000- simc1 1000 0001 1000 0001 1000 0001 1000 0001 uuuu uuuu 1000 0001 1000 0001 simd xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx sim?/simc? 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 spi?c0 111- --0- 111- --0- 111- --0- 111- --0- uuu- --u- 111- --0- 111- --0- spi?c1 --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 spi?d xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx sbsc 0-00 ---0 0-00 ---0 0-00 ---0 0-00 ---0 u-uu ---u 0-00 ---0 0-00 ---0 p? wu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 p ?dir 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 p ?pu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pxpu 0000 --00 0000 --00 0000 --00 0000 --00 uuuu --uu 0000 --00 0000 --00 p ?oi 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pslew 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pxwu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pxoi 0000 --00 0000 --00 0000 --00 0000 --00 uuuu --uu 0000 --00 0000 --00 cp0c 1000 0--1 1000 0--1 1000 0--1 1000 0--1 uuuu u--u 1000 0--1 1000 0--1 cp1c 1000 0--1 1000 0--1 1000 0--1 1000 0--1 uuuu u--u 1000 0--1 1000 0--1 tmpc0 --01 --01 --01 --01 --01 --01 --01 --01 --uu --uu --01 --01 --01 --01 tmpc1 --0- --0- --0- --0- --0- --0- --0- --0- --u- --u- --0- --0- --0- --0- tm0c0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- 0000 0--- 0000 0--- tm0c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm0dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm0dh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm0?l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm0?h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm0rp 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm1c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm1c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm1dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm1dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 tm1?l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm1?h ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 tm?c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 tm??l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm??h ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00
rev. 1.00 80 ???i? 0?? ?01? rev. 1.00 81 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi register reset (power on) wdt time-out/ wdtc software reset (normal operation) res reset/ lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) tm?c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 tm??l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm??h ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 usb_st ? t 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- uint ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 usc 1000 0000 uuuu xuux 1000 0000 1000 0000 uuuu xuux 1uuu 0100 1uuu 0100 usr ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 ucc 0000 0-00 uuuu u-uu 0000 0-00 0000 0-00 uuuu u-uu 0uu0 u-00 0uu0 u-00 ? wr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 stli ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 stlo ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 sies 00-0 0000 uu-x xuuu 00-0 0000 00-0 0000 uu-x xuuu 00-0 0000 00-0 0000 misc 000- 0000 xxu- uuuu 000- 0000 000- 0000 xxu- uuuu 000- 0000 000- 0000 ufien ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 fifo0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo? xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo? xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ufoen ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 ufc0 0000 00-- uuuu uu-- 0000 00-- 0000 00-- uuuu uu-- 0000 00-- 0000 00-- p ?ps0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 p ?ps1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 sysc 000- -0-- 000- -0-- 000- -0-- 000- -0-- uuu- -u-- 000- -0-- 000- -0-- ctrl 0--- -x00 0--- -x00 0--- -x00 0--- -x00 u--- -xuu 0--- -x00 0--- -x00 lvrc 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu 0101 0101 0101 0101 note: * stands for warm reset - not implement u stands for unchanged x stands for unknown
rev. 1.00 8? ???i? 0?? ?01? rev. 1.00 8? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi the ht66fb550 register states are summarized below: register reset (power on) wdt time-out/ wdtc software reset (normal operation) res reset/ lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) mp0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx mp1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ?cc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tbhp ---x xxxx ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu st ? tus --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu --uu uuuu --uu uuuu bp ---- -000 ---- --000 ---- -000 ---- -000 ---- -uuu ---- -000 ---- -000 smod 0000 0011 0000 0011 0000 0011 0000 0011 uuuu uuuu 0000 0011 0000 0011 integ 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 lvdc --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu --00 -000 --00 -000 intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 intc1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 intc? 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 intc? -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu -000 -000 -000 -000 mfi0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 mfi1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 mfi? -0-0 -0-0 -0-0 -0-0 -0-0 -0-0 -0-0 -0-0 -u-u -u-u -0-0 -0-0 -0-0 -0-0 p? 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 p? c 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pe --11 1101 --11 1101 --11 1101 --11 1101 --uu uuuu --11 1101 --11 1101 pec --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu --11 1111 --11 1111 ?drl (?drfs=0) xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- xxxx ---- xxxx ---- ?drl (?drfs=1) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ?drh (?drfs=0) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ?drh (?drfs=1) ---- xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- xxxx ---- xxxx ?dcr0 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu 0110 0000 0110 0000 ?dcr1 00-0 -000 00-0 -000 00-0 -000 00-0 -000 uu-u -uuu 00-0 -000 00-0 -000 ?cer0 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 ?cer1 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 wdtc 0101 0011 0101 0011 0101 0011 0101 0011 uuuu uuuu 0101 0011 0101 0011 tbc 0011 0111 0011 0111 0011 0111 0011 0111 uuuu uuuu 0011 0111 0011 0111 frcr ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u ---0 ---0 ---0 ---0 fcr 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 f ?rl xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx
rev. 1.00 8? ???i? 0?? ?01? rev. 1.00 8? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi register reset (power on) wdt time-out/ wdtc software reset (normal operation) res reset/ lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) f ?rh ---x xxxx ---x xxxx ---x xxxx ---x xxxx ---u uuuu ---x xxxx ---x xxxx fd0l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd0h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd?l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd?h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd?l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd?h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx i? ctoc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 simc0 1110 000- 1110 000- 1110 000- 1110 000- uuuu uuu- 1110 000- 1110 000- simc1 1000 0001 1000 0001 1000 0001 1000 0001 uuuu uuuu 1000 0001 1000 0001 simd xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx sim ? /simc? 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 spi?c0 111- --0- 111- --0- 111- --0- 111- --0- uuu- --u- 111- --0- 111- --0- spi?c1 --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 spi?d xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx sbsc 0-00 ---0 0-00 ---0 0-00 ---0 0-00 ---0 u-uu ---u 0-00 ---0 0-00 ---0 p? wu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 p ?dir 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 p ?pu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pxpu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 p ?oi 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pslew 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pxwu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pxoi 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 cp0c 1000 0--1 1000 0--1 1000 0--1 1000 0--1 uuuu u--u 1000 0--1 1000 0--1 cp1c 1000 0--1 1000 0--1 1000 0--1 1000 0--1 uuuu u--u 1000 0--1 1000 0--1 tmpc0 --01 --01 --01 --01 --01 --01 --01 --01 --uu --uu --01 --01 --01 --01 tmpc1 --01 --01 --01 --01 --01 --01 --01 --01 --uu --uu --01 --01 --01 --01 tm0c0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- 0000 0--- 0000 0--- tm0c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm0dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm0dh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm0?l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm0?h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm0rp 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm1c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm1c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm1dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm1dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 tm1?l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm1?h ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 tm?c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000
rev. 1.00 84 ???i? 0?? ?01? rev. 1.00 85 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi register reset (power on) wdt time-out/ wdtc software reset (normal operation) res reset/ lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) tm?dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 tm??l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm??h ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 tm?c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 tm??l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm??h ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 usb_st ? t 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- uint --00 0000 --uu uuuu --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 usc 1000 0000 uuuu xuux 1000 0000 1000 0000 uuuu xuux 1uuu 0100 1uuu 0100 usr --00 0000 --uu uuuu --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 ucc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0uu0 u000 0uu0 u000 ? wr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 stli --00 0000 --uu uuuu --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 stlo --00 0000 --uu uuuu --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 sies 00-0 0000 uu-x xuuu 00-0 0000 00-0 0000 uu-x xuuu 00-0 0000 00-0 0000 misc 0000 0000 xxuu uuuu 0000 0000 0000 0000 xxuu uuuu 0000 0000 0000 0000 ufien --00 0000 --uu uuuu --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 fifo0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo? xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo? xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo4 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo5 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ufoen --00 0000 --uu uuuu --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 ufc0 0000 00-- uuuu uu-- 0000 00-- 0000 00-- uuuu uu-- 0000 00-- 0000 00-- ufc1 ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 p ?ps0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 p ?ps1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 sysc 000- -0-- 000- -0-- 000- -0-- 000- -0-- uuu- -u-- 000- -0-- 000- -0-- ctrl 0--- -x00 0--- -x00 0--- -x00 0--- -x00 u--- -xuu 0--- -x00 0--- -x00 lvrc 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu 0101 0101 0101 0101 note: * stands for warm reset - not implement u stands for unchanged x stands for unknown
rev. 1.00 84 ???i? 0?? ?01? rev. 1.00 85 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi the ht66fb560 register states are summarized below: register reset (power on) wdt time-out/ wdtc software reset (normal operation) res reset/ lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) mp0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx mp1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ?cc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tbhp --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu --uu uuuu --uu uuuu st ? tus --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu --uu uuuu --uu uuuu bp --0- -000 --0- --000 --0- -000 --0- -000 --u- -uuu --0- -000 --0- -000 smod 0000 0011 0000 0011 0000 0011 0000 0011 uuuu uuuu 0000 0011 0000 0011 integ 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 lvdc --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu --00 -000 --00 -000 intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 intc1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 intc? 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 intc? -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu -000 -000 -000 -000 mfi0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 mfi1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 mfi? -0-0 -0-0 -0-0 -0-0 -0-0 -0-0 -0-0 -0-0 -u-u -u-u -0-0 -0-0 -0-0 -0-0 p? 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 p? c 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pe --11 1101 --11 1101 --11 1101 --11 1101 --uu uuuu --11 1101 --11 1101 pec --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu --11 1111 --11 1111 pf 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pfc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 ?drl (?drfs=0) xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- xxxx ---- xxxx ---- ?drl (?drfs=1) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ?drh (?drfs=0) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ?drh (?drfs=1) ---- xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- xxxx ---- xxxx ?dcr0 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu 0110 0000 0110 0000 ?dcr1 00-0 -000 00-0 -000 00-0 -000 00-0 -000 uu-u -uuu 00-0 -000 00-0 -000 ?cer0 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 ?cer1 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 wdtc 0101 0011 0101 0011 0101 0011 0101 0011 uuuu uuuu 0101 0011 0101 0011 tbc 0011 0111 0011 0111 0011 0111 0011 0111 uuuu uuuu 0011 0111 0011 0111 frcr ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u ---0 ---0 ---0 ---0
rev. 1.00 86 ???i? 0?? ?01? rev. 1.00 87 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi register reset (power on) wdt time-out/ wdtc software reset (normal operation) res reset/ lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) fcr 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 f ?rl xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx f ?rh --xx xxxx --xx xxxx --xx xxxx --xx xxxx --uu uuuu --xx xxxx --xx xxxx fd0l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd0h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd?l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd?h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd?l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx fd?h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx i? ctoc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 simc0 1110 000- 1110 000- 1110 000- 1110 000- uuuu uuu- 1110 000- 1110 000- simc1 1000 0001 1000 0001 1000 0001 1000 0001 uuuu uuuu 1000 0001 1000 0001 simd xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx sim?/simc? 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 spi?c0 111- --0- 111- --0- 111- --0- 111- --0- uuu- --u- 111- --0- 111- --0- spi?c1 --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 spi?d xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx sbsc 0-00 ---0 0-00 ---0 0-00 ---0 0-00 ---0 u-uu ---u 0-00 ---0 0-00 ---0 p? wu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 p ?dir 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 p ?pu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pxpu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 p ?oi 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pslew 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pxwu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pxoi 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pfpu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pfwu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 cp0c 1000 0--1 1000 0--1 1000 0--1 1000 0--1 uuuu u--u 1000 0--1 1000 0--1 cp1c 1000 0--1 1000 0--1 1000 0--1 1000 0--1 uuuu u--u 1000 0--1 1000 0--1 tmpc0 --01 --01 --01 --01 --01 --01 --01 --01 --uu --uu --01 --01 --01 --01 tmpc1 --01 --01 --01 --01 --01 --01 --01 --01 --uu --uu --01 --01 --01 --01 tm0c0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- 0000 0--- 0000 0--- tm0c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm0dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm0dh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm0?l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm0?h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm1c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm1c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm1dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm1dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 tm1?l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm1?h ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00
rev. 1.00 86 ???i? 0?? ?01? rev. 1.00 87 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi register reset (power on) wdt time-out/ wdtc software reset (normal operation) res reset/ lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) tm?c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 tm??l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm??h ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 tm?c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm?dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 tm??l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tm??h ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 usb_st ? t 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- uint 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 usc 1000 0000 uuuu xuux 1000 0000 1000 0000 uuuu xuux 1uuu 0100 1uuu 0100 usr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ucc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0uu0 u000 0uu0 u000 ? wr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 stli 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 stlo 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 sies 00-0 0000 uu-x xuuu 00-0 0000 00-0 0000 uu-x xuuu 00-0 0000 00-0 0000 misc 0000 0000 xxuu uuuu 0000 0000 0000 0000 xxuu uuuu 0000 0000 0000 0000 ufien 0000 0000 00uu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 fifo0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo? xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo? xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo4 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo5 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo6 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo7 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ufoen 0000 0000 00uu uuuu -0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ufc0 0000 00-- uuuu uu-- 0000 00-- 0000 00-- uuuu uu-- 0000 00-- 0000 00-- ufc1 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 p ?ps0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 p ?ps1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 sysc 000- -0-- 000- -0-- 000- -0-- 000- -0-- uuu- -u-- 000- -0-- 000- -0-- ctrl 0--- -x00 0--- -x00 0--- -x00 0--- -x00 u--- -xuu 0--- -x00 0--- -x00 lvrc 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu 0101 0101 0101 0101 note: * stands for warm reset - not implement u stands for unchanged x stands for unknown
rev. 1.00 88 ???i? 0?? ?01? rev. 1.00 89 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi input/output ports holtek microcontrollers offer considerable fexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the devices provides bidirectional input/output lines labeled with port names pa~pf these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list ? HT66FB540 register name bit 7 6 5 4 3 2 1 0 p? wu d7 d6 d5 d4 d? d? d1 d0 p ?pu d7 d6 d5 d4 d? d? d1 d0 p? d7 d6 d5 d4 d? d? d1 d0 p? c d7 d6 d5 d4 d? d? d1 d0 p ?dir d7 d6 d5 d4 d? d? d1 d0 p ?oi d7 d6 d5 d4 d? d? d1 d0 pslew pdslew1 pdslew0 pbslew1 pbslew0 p ?slew1 p ?slew0 pxwu pehwu pelwu pdhwu pdlwu pbhwu pblwu pxpu pehpu pelpu pdhpu pdlpu pbhpu pblpu pxoi pehi peli pdhi pdli pbhi pbli p ?ps0 p ??s1 p ??s0 p ??s1 p ??s0 p ?1s1 p ?1s0 p ?0s1 p ?0s0 p ?ps1 p ?7s1 p ?7s0 p ?6s1 p ?6s0 p ?5s1 p ?5s0 p ?4s1 p ?4s0 pb d6 d5 d4 d? d? d1 d0 pbc d6 d5 d4 d? d? d1 d0 pd d5 d4 d? d? d1 d0 pdc d5 d4 d? d? d1 d0 pe d4 d? d? d1 d0 pec d4 d? d? d1 d0
rev. 1.00 88 ???i? 0?? ?01? rev. 1.00 89 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb550 register name bit 7 6 5 4 3 2 1 0 p? wu d7 d6 d5 d4 d? d? d1 d0 p ?pu d7 d6 d5 d4 d? d? d1 d0 p? d7 d6 d5 d4 d? d? d1 d0 p? c d7 d6 d5 d4 d? d? d1 d0 p ?dir d7 d6 d5 d4 d? d? d1 d0 p ?oi d7 d6 d5 d4 d? d? d1 d0 pslew pdslew1 pdslew0 pcslew1 pcslew0 pbslew1 pbslew0 p ?slew1 p ?slew0 pxwu pehwu pelwu pdhwu pdlwu pchwu pclwu pbhwu pblwu pxpu pehpu pelpu pdhpu pdlpu pchpu pclpu pbhpu pblpu pxoi pehi peli pdhi pdli pchi pcli pbhi pbli p ?ps0 p ??s1 p ??s0 p ??s1 p ??s0 p ?1s1 p ?1s0 p ?0s1 p ?0s0 p ?ps1 p ?7s1 p ?7s0 p ?6s1 p ?6s0 p ?5s1 p ?5s0 p ?4s1 p ?4s0 pb d7 d6 d5 d4 d? d? d1 d0 pbc d7 d6 d5 d4 d? d? d1 d0 pc d7 d6 d5 d4 d? d? d1 d0 pcc d7 d6 d5 d4 d? d? d1 d0 pd d7 d6 d5 d4 d? d? d1 d0 pdc d7 d6 d5 d4 d? d? d1 d0 pe d5 d4 d? d? d1 d0 pec d5 d4 d? d? d1 d0
rev. 1.00 90 ???i? 0?? ?01? rev. 1.00 91 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb560 register name bit 7 6 5 4 3 2 1 0 p? wu d7 d6 d5 d4 d? d? d1 d0 p ?pu d7 d6 d5 d4 d? d? d1 d0 p? d7 d6 d5 d4 d? d? d1 d0 p? c d7 d6 d5 d4 d? d? d1 d0 p ?dir d7 d6 d5 d4 d? d? d1 d0 p ?oi d7 d6 d5 d4 d? d? d1 d0 pslew pdslew1 pdslew0 pcslew1 pcslew0 pbslew1 pbslew0 p ?slew1 p ?slew0 pxwu pehwu pelwu pdhwu pdlwu pchwu pclwu pbhwu pblwu pxpu pehpu pelpu pdhpu pdlpu pchpu pclpu pbhpu pblpu pxoi pehi peli pdhi pdli pchi pcli pbhi pbli p ?ps0 p ??s1 p ??s0 p ??s1 p ??s0 p ?1s1 p ?1s0 p ?0s1 p ?0s0 p ?ps1 p ?7s1 p ?7s0 p ?6s1 p ?6s0 p ?5s1 p ?5s0 p ?4s1 p ?4s0 pb d7 d6 d5 d4 d? d? d1 d0 pbc d7 d6 d5 d4 d? d? d1 d0 pc d7 d6 d5 d4 d? d? d1 d0 pcc d7 d6 d5 d4 d? d? d1 d0 pd d7 d6 d5 d4 d? d? d1 d0 pdc d7 d6 d5 d4 d? d? d1 d0 pe d5 d4 d? d? d1 d0 pec d5 d4 d? d? d1 d0 pfwu d7 d6 d5 d4 d? d? d1 d0 pfpu d7 d6 d5 d4 d? d? d1 d0 pf d7 d6 d5 d4 d? d? d1 d0 pfc d7 d6 d5 d4 d? d? d1 d0
rev. 1.00 90 ???i? 0?? ?01? rev. 1.00 91 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using registers, namely papu, pxpu and pfpu, and are implemented using weak pmos transistors. note that the pa and pf pull-high resistors are controlled by bits in the papu and pfpu registers, other than the pb, pc, pd, pe pull-high resistors are controlled by nibble in the pxpu register. papu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 i/o pa bit 7~bit 0 pull-high control 0: disable 1: enable pxpu register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name pehpu pelpu pdhpu pdlpu pbhpu pblpu r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pehpu: pe4 pins pull-high control 0: disable 1: enable bit 6 pelpu: pe3, pe2 and pe0 pins pull-high control 0: disable 1: enable note that the pe1 pin has no pull-up resistor. bit 5 pdhpu: pd7~pd4 pins pull-high control 0: disable 1: enable bit 4 pdlpu: pd3~pd0 pins pull-high control 0: disable 1: enable bit 3~2 unimplemented bit 1 pbhpu: pb6~pb4 pins pull-high control 0: disable 1: enable bit 0 pblpu: pb3~pb0 pins pull-high control 0: disable 1: enable
rev. 1.00 9? ???i? 0?? ?01? rev. 1.00 9? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb550/ht66fb560 bit 7 6 5 4 3 2 1 0 name pehpu pelpu pdhpu pdlpu pchpu pclpu pbhpu pblpu r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pehpu: pe5~pe4 pins pull-high control 0: disable 1: enable bit 6 pelpu: pe3, pe2 and pe0 pins pull-high control 0: disable 1: enable note that the pe1 pin has no pull-up resistor. bit 5 pdhpu: pd7~pd4 pins pull-high control 0: disable 1: enable bit 4 pdlpu: pd3~pd0 pins pull-high control 0: disable 1: enable bit 3 pchpu: pc7~pc4 pins pull-high control 0: disable 1: enable bit 2 pclpu: pc3~pc0 pins pull-high control 0: disable 1: enable bit 1 pbhpu: pb7~pb4 pins pull-high control 0: disable 1: enable bit 0 pblpu: pb3~pb0 pins pull-high control 0: disable 1: enable pfpu register ? ht66fb560 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 i/o port f bit 7~bit 0 pull-high control 0: disable 1: enable
rev. 1.00 9? ???i? 0?? ?01? rev. 1.00 9? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi port wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a~port f pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a~portf can be selected by bits or nibble to have this wake-up feature using the pawu, pxwu and pfwu registers. pawu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pawu: port a bit 7~bit 0 wake-up control 0: disable 1: enable pxwu register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name pehwu pelwu pdhwu pdlwu pbhwu pblwu r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pehwu: pe4 pins wake-up control 0: disable 1: enable bit 6 pelwu: pe3, pe2,pe0 pins wake-up control 0: disable 1: enable note that the pe1 pin has no wake-up function. bit 5 pdhwu: pd7~pd4 pins wake-up control 0: disable 1: enable bit 4 pdlwu: pd3~pd0 pins wake-up control 0: disable 1: enable bit3~2 unimplemented bit 1 pbhwu: pb6~pb4 pins wake-up control 0: disable 1: enable bit 0 pblwu: pb3~pb0 pins wake-up control 0: disable 1: enable
rev. 1.00 94 ???i? 0?? ?01? rev. 1.00 95 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb550/ht66fb560 bit 7 6 5 4 3 2 1 0 name pehwu pelwu pdhwu pdlwu pchwu pclwu pbhwu pblwu r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pehwu: pe5, pe4 pins wake-up control 0: disable 1: enable bit 6 pelwu: pe3~pe2, pe0 pins wake-up control 0: di sable 1: enable note that the pe1 pin has no wake-up function. bit 5 pdhwu: pd7~pd4 pins wake-up control 0: disable 1: enable bit 4 pdlwu: pd3~pd0 pins wake-up control 0: disable 1: enable bit 3 pchwu: pc7~pc4 pins wake-up control 0: disable 1: enable bit 2 pclwu: pc3~pc0 pins wake-up control 0: disable 1: enable bit 1 pbhwu: pb7~pb4 pins wake-up control 0: disable 1: enable bit 0 pblwu: pb3~pb0 pins wake-up control 0: disable 1: e nable pfwu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pfwu: port a bit 7~bit 0 wake-up control 0: disable 1: enable port a wake-up polarity control register the i/o port, pa, can be setup to have a choice of wake-up polarity using specifc register. each pin on port a can be selected individually to have this wake-up polarity feature using the padir register. padir register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 padir: pa7~pa0 pins wake-up edge control 0: rising edge 1: falling edge
rev. 1.00 94 ???i? 0?? ?01? rev. 1.00 95 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi i/o port control registers each i/o port has its own control register known as pac~pfc, to control the input/output configuration. with this control register, each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pbc register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 ? ht66fb550/ht66fb560 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pcc register ? ht66fb550/ht66fb560 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1
rev. 1.00 96 ???i? 0?? ?01? rev. 1.00 97 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi pdc register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 ? ht66fb550/ht66fb560 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pec register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 ? ht66fb550/ht66fb560 bit 7 6 5 4 3 2 1 0 name d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 pfc register ? ht66fb560 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 i/o port bit 7~bit 0 input/output control 0: output 1: input
rev. 1.00 96 ???i? 0?? ?01? rev. 1.00 97 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi i/o output current control registers the i/o ports, pa~pe, can be setup to have a choice of high or low drive currents using specifc registers. each pin on port a can be selected individually to have this high output current feature using the paoi register. as for pb~pe, the output current must be selected by nibble using the pxoi register. note that the port f is defaulted to have a low output current, the i ol is 4ma and i oh is -4ma at v dd = 5 v. paoi register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pa7~pa0 pins output current control (typical value, at v dd =5v) 0: i ol /i oh low current drive 1: i ol /i oh high current drive pxoi register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name pehi peli pdhi pdli pbhi pbli r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pe4 pin output current control (typical value, at v dd =5v) 0: i ol /i oh low current drive 1: i ol /i oh high current drive bit 6 pe3~pe0 pins output current control (typical value, at v dd =5v) 0: i ol /i oh low current drive 1: i ol /i oh high current drive bit 5 pd5~pd4 pins output current control (typical value, at v dd =5v) 0: i ol /i oh low current drive 1: i ol /i oh high current drive bit 4 pd3~pd0 pins output current control (typical value, at v dd =5v) 0: i ol /i oh low current drive 1: i ol /i oh high current drive bit 3, 2 unimplemented bit 1 pb6~pb4 pins output current control (typical value, at v dd =5v) 0: i ol /i oh low current drive 1: i ol /i oh high current drive bit 0 pb3~pb0 pins output current control (typical value, at v dd =5v) 0: i ol /i oh low current drive 1: i ol /i oh high current drive
rev. 1.00 98 ???i? 0?? ?01? rev. 1.00 99 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb550/ht66fb560 bit 7 6 5 4 3 2 1 0 name pehi peli pdhi pdli pchi pcli pbhi pbli r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pehi: pe5~pe4 pins output current control (typical value, at v =5v) 0: i ol low current drive 1: i ol high current drive bit 6 peli: pe3~pe0 pins output current control (typical value, at v =5v) 0: i ol low current drive 1: i ol high current drive bit 5 pdhi: pd7~pd4 pins output current control (typical value, at v =5v) 0: i ol low current drive 1: i ol high current drive bit 4 pdli: pd3~pd0 pins output current control (typical value, at v =5v) 0: i ol low current drive 1: i ol high current drive bit 3 pchi: pc7~pc4 pins output current control (typical value, at v =5v) 0: i ol low current drive 1: i ol high current drive bit 2 pcli: pc3~pc0 pins output current control (typical value, at v =5v) 0: i ol low current drive 1: i ol high current drive bit 1 pbhi: pb7~pb4 pins output current control (typical value, at v =5v) 0: i ol low current drive 1: i ol high current drive bit 0 pbli: pb3~pb0 pins output current control (typical value, at v =5v) 0: i ol low current drive 1: i ol high current drive i/o output slew rate control registers the i/o ports, pa~pd, can be setup to have a choice of various slew rate using specifc registers. the slew rate must be selected by nibble using the pslew register. note that the port e and the port f are defaulted to have a fxed slew rate at 200ns.
rev. 1.00 98 ???i? 0?? ?01? rev. 1.00 99 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi pslew register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name pdslew1 pdslew0 pbslew1 pbslew0 p ?slew1 p ?slew0 r/w r/w r/w 0 0 r/w r/w r/w r/w por 0 0 r r 0 0 0 0 bit 7, 6 pdslew1, pdslew0: port d output slew rate control 00: 200ns 01: 100ns 10: 50ns 11: no slew rate bit 5, 4 unimplemented bit 3, 2 pbslew1, pbslew0: port b output slew rate control 00: 200ns 01: 100ns 10: 50ns 11: no slew rate bit 1, 0 paslew1, paslew0: port a output slew rate control 00: 200ns 01: 100ns 10: 50ns 11: no slew rate ? ht66fb550/ht66fb560 bit 7 6 5 4 3 2 1 0 name pdslew1 pdslew0 pcslew1 pcslew0 pbslew1 pbslew0 p ?slew1 p ?slew0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7, 6 pdslew1, pdslew0: port d output slew rate control 00: 200ns 01: 100ns 10: 50ns 11: no slew rate bit 5, 4 pcslew1, pcslew0: port c output slew rate control 00: 200ns 01: 100ns 10: 50ns 11: no slew rate bit 3, 2 pbslew1, pbslew0: port b output slew rate control 00: 200ns 01: 100ns 10: 50ns 11: no slew rate bit 1, 0 paslew1, paslew0: port a output slew rate control 00: 200ns 01: 100ns 10: 50ns 11: no slew rate
rev. 1.00 100 ???i? 0?? ?01? rev. 1.00 101 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi port a power source control registers port a can be setup to have a choice of various power source using specifc registers. each pin on port a can be selected individually to have various power sources using the paps0 and paps1 registers. paps0 register bit 7 6 5 4 3 2 1 0 name p ??s1 p ??s0 p ??s1 p ??s0 p ?1s1 p ?1s0 p ?0s1 p ?0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7, 6 pa3s1, pa3s0: pa3 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output bit 5, 4 pa2s1, pa2s0: pa2 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output bit 3, 2 pa1s1, pa1s0: pa1 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output bit 1, 0 pa0s1, pa0s0: pa0 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output paps1 register bit 7 6 5 4 3 2 1 0 name p ?7s1 p ?7s0 p ?6s1 p ?6s0 p ?5s1 p ?5s0 p ?4s1 p ?4s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7, 6 pa7s1, pa7s0: pa7 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output bit 5, 4 pa6s1, pa6s0: pa6 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output bit 3, 2 pa5s1, pa5s0: pa5 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output
rev. 1.00 100 ???i? 0?? ?01? rev. 1.00 101 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi bit 1, 0 pa4s1, pa4s0: pa4 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

??? ? ? ? generic input/output structure

? ?
? ? ? ? - ? ? - ? ? ? ? a/d input/output structure
rev. 1.00 10? ???i? 0?? ?01? rev. 1.00 10? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi programming considerations within the user program, one of the frst things to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers, pac~pfc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, pa~pf, are first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. all ports provide the wake-up function which can be set by individual pin in the port a and port f while it has to be set by nibble pins in the port b, port c, port d and port e. when the devices are in the sleep or idle mode, various methods are available to wake the devices up. one of these is a high to low transition of any of the port pins. single or multiple pins on ports can be setup to have this function.
rev. 1.00 10? ???i? 0?? ?01? rev. 1.00 10? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi timer modules C tm one of the most fundamental functions in any microcontroller devices are the ability to control and measure time. to implement time related functions each device includes several timer modules, abbreviated to the name tm. the tms are multi-purpose timing units and serve to provide operations such as timer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has either two or three individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the different tm types are described here with more detailed information provided in the individual compact and standard tm sections. introduction the devices contain four tms having a reference name of tm0, tm1, tm2 and tm3. each individual tm can be categorised as a certain type, namely compact type tm or standard type tm. although similar in nature, the different tm types vary in their feature complexity. the common features to all of the compact and standard tms will be described in this section. the detailed operation regarding each of the tm types will be described in separate sections. the main features and differences between the two types of tms are summarised in the accompanying table. function ctm stm time ?/counte? i/p ca ?tu?e com?a?e match out?ut pwm channe?s 1 1 sing?e pu?se out?ut 1 pwm ??ignment edge edge pwm ?djustment pe?iod & duty duty o? pe?iod duty o? pe?iod tm function summary each device in the series contains a specifc number of either compact type and standard type tm units which are shown in the table together with their individual reference name, tm0~tm3. device tm0 tm1 tm2 tm3 HT66FB540/ht66fb550/ ht66fb560 16-bit stm 10-bit stm 10-bit ctm 10-bit ctm tm name/type reference tm operation the different types of tm offer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin.
rev. 1.00 104 ???i? 0?? ?01? rev. 1.00 105 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. note that setting these bits to the value 101 will select an undefned clock input, in effect disconnecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact and standard type tms each have two internal interrupts, one for each of the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register. this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected using the tnck2~tnck0 bits. the tm input pin can be chosen to have either a rising or falling active edge. the tms each have one or more output pins with the label tpn. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must first be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type and devices are different, the details are provided in the accompanying table. all tm output pin names have a _n suffx. pin names that include a _0 or _1 suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. device ctm stm registers HT66FB540 tp?_1? tp?_1 tp0_0? tp0_1 tp1_0? tp1_1 tmpc0? tmpc1 ht66fb550? ht66fb560 tp?_0? tp?_0 tp?_1? tp?_1 tm output pins
rev. 1.00 104 ???i? 0?? ?01? rev. 1.00 105 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi tm input/output pin control registers selecting to have a tm input/output or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function. registers device bit 7 6 5 4 3 2 1 0 tmpc0 HT66FB540 ht66fb550 ht66fb560 t1cp1 t1cp0 t0cp1 t0cp0 tmpc1 HT66FB540 t?cp1 t?cp1 tmpc1 ht66fb550 ht66fb560 t?cp1 t?cp0 t?cp1 t?cp0 tm input/output pin control registers list
HT66FB540/ht66fb550/ht66fb560 tm0 function pin control block diagram note: (1) the i/o register data bits shown are used for tm output inversion control. (2) in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.00 106 ???i? 0?? ?01? rev. 1.00 107 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi

HT66FB540/ht66fb550/ht66fb560 tm1 function pin control block diagram note: (1) the i/o register data bits shown are used for tm output inversion control. (2) in the capture input mode, the tm pin control register must never enable more than one tm input. HT66FB540 tm2 function pin control block diagram note: (1) the i/o register data bits shown are used for tm output inversion control. (2) in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.00 106 ???i? 0?? ?01? rev. 1.00 107 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi

ht66fb550/ht66fb560 tm2 function pin control block diagram note: (1) the i/o register data bits shown are used for tm output inversion control. (2) in the capture input mode, the tm pin control register must never enable more than one tm input.
HT66FB540 tm3 function pin control block diagram note: (1) the i/o register data bits shown are used for tm output inversion control. (2) in the capture input mode, the tm pin control register must never enable more than one tm input.

ht66fb550/ht66fb560 tm3 function pin control block diagram note: (1) the i/o register data bits shown are used for tm output inversion control. (2) in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.00 108 ???i? 0?? ?01? rev. 1.00 109 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi tmpc0 register bit 7 6 5 4 3 2 1 0 name t1cp1 t1cp0 t0cp1 t0cp0 r/w r r r/w r/w r r r/w r/w por 0 0 0 1 0 0 0 1 bit 7~6 unimplemented bit 5 t1cp1: tp1_1 pin control 0: disable 1: enable bit 4 t1cp0: tp1_0 pin control 0: disable 1: enable bit 3~2 unimplemented bit 1 t0cp1: tp0_1 pin control 0: disable 1: enable bit 0 t0cp0: tp0_0 pin control 0: disable 1: enable tmpc1 register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name t?cp1 t?cp1 r/w r r r/w r r r r/w r por 0 0 0 0 0 0 0 0 bit 7~6 unimplemented bit 5 t3cp1: tp3_1 pin control 0: disable 1: enable bit 4~2 unimplemented bit 1 t2cp1: tp2_1 pin control 0: disable 1: enable bit 0 unimplemented
rev. 1.00 108 ???i? 0?? ?01? rev. 1.00 109 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb550/ht66fb560 bit 7 6 5 4 3 2 1 0 name t?cp1 t?cp0 t?cp1 t?cp0 r/w r r r/w r/w r r r/w r/w por 0 0 0 1 0 0 0 1 bit 7~6 unimplemented bit 5 t3cp1: tp3_1 pin control 0: disable 1: enable bit 4 t3cp0: tp3_0 pin control 0: disable 1: enable bit 3~2 unimplemented bit 1 t2cp1: tp2_1 pin control 0: disable 1: enable bit 0 t2cp0: tp2_0 pin control 0: disable 1: enable programming considerations the tm counter registers and the capture/compare ccra register, being either 10-bit or 16-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. data bus 8 - bit buffe? tmxdh tmxdl tmxbh tmxbl tmxah tmx?l tm counte? registe? ( read on?y ) tm ccr? registe? ( read / w?ite ) tm ccrb registe? ( read / w?ite )
rev. 1.00 110 ???i? 0?? ?01? rev. 1.00 111 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi the following steps show the read and write procedures: ? writing data to ccra ? step 1. write data to low byte tmxal C note that here data is only written to the 8-bit buffer. ? step 2. write data to high byte tmxah C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and or ccra ? step 1. read data from the high byte tmxdh, tmxah C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal C this step reads data from the 8-bit buffer. as the ccra register is implemented in the way shown in the following diagram and accessing the register pair is carried out in a specifc way described above, it is recommended to use the mov instruction to access the ccra low byte register, named tmxal, using the following access procedures. accessing the ccra low byte register without following these access procedures will result in unpredictable values. compact type tm C ctm although the simplest form of the two tm types, the compact tm type still contains three operating modes, which are compare match output, timer/event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive two external output pins. these two external output pins can be the same signal or the inverse signal. ctm name tm no. tm input pin tm output pin HT66FB540 10-bit ctm ?? ? tck?? tck? tp?_1? tp?_1? ht66fb550/ ht66fb560 10-bit ctm ?? ? tck?? tck? tp?_0? tp?_1? tp?_0? tp?_1?
? ? ? ? ? ? ? ? ? ?
? ?
? ?

? ? ?
? - - ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ??? ?? compact type tm block diagram
rev. 1.00 110 ???i? 0?? ?01? rev. 1.00 111 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. compact type tm register description overall operation of the compact tm is controlled using six registers. a read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmnc0 tnp ?u tnck? tnck1 tnck0 tnon tnrp? tnrp1 tnrp0 tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr tmndl d7 d6 d5 d4 d? d? d1 d0 tmndh d9 d8 tmn?l d7 d6 d5 d4 d? d? d1 d0 tmn?h d9 d8 compact tm register list (n=2, 3) tmndl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tmndl: tmn counter low byte register bit 7~bit 0 tmn 10-bit counter bit 7~bit 0 tmndh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented bit 1~0 tmndh: tmn counter high byte register bit 1~bit 0 tmn 10-bit counter bit 9~bit 8
rev. 1.00 11 ? ???i? 0?? ?01? rev. 1.00 11 ? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi tmnal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnal: tmn ccra low byte register bit 7~bit 0 tmn 10-bit ccra bit 7~bit 0 tmnah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented bit 1~0 tmnah: tmn ccra high byte register bit 1~bit 0 tmn 10-bit ccra bit 9~bit 8 tmnc0 register bit 7 6 5 4 3 2 1 0 name tnp ?u tnck? tnck1 tnck0 tnon tnrp? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau: tmn counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0: select tmn counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefned 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tmn. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section.
rev. 1.00 11 ? ???i? 0?? ?01? rev. 1.00 11 ? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi bit 3 tnon: tmn counter on/off control 0: off 1: on this bit controls the overall on/off function of the tmn. setting the bit high enables the counter to run, clearing the bit disables the tmn. clearing this bit to zero will stop the counter from counting and turn off the tmn which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. if the tmn is in the compare match output mode then the tmn output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 tnrp2~tnrp0: tmn ccrp 3-bit register, compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counters highest three bits. the result of this comparison can be selected to clear the internal counter if the tncclr bit is set to zero. setting the tncclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
rev. 1.00 114 ???i? 0?? ?01? rev. 1.00 115 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi tmnc1 register bit 7 6 5 4 3 2 1 0 name tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0: select tmn operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the tnm1 and tnm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0: select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determine how the tmn output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tmn is running. in the compare match output mode, the tnio1 and tnio0 bits determine how the tmn output pin changes state when a compare match occurs from the comparator a. the tmn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tmn output pin should be setup using the tnoc bit in the tmnc1 register. note that the output level requested by the tnio1 and tnio0 bits must be different from the initial value setup using the tnoc bit otherwise no change will occur on the tmn output pin when a compare match occurs. after the tmn output pin changes state it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the values of the tnio1 and tnio0 bits only after the tmn has been switched off. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running.
rev. 1.00 114 ???i? 0?? ?01? rev. 1.00 115 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi bit 3 tnoc: tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tmn output pin. its operation depends upon whether tmn is being used in the compare match output mode or in the pwm mode. it has no effect if the tmn is in the timer/counter mode. in the compare match output mode it determines the logic level of he tmn output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 tnpol: tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0 or tpn_1 output pin. when the bit is set high the tmn output pin will be inverted and not inverted when the bit is zero. it has no effect if the tmn is in the timer/counter mode. bit 1 tndpx: tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 tncclr: select tmn counter clear condition 0: tmn comparator p match 1: tmn comparator a match this bit is used to select the method which clears the counter. remember that the compact tmn contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode.
rev. 1.00 116 ???i? 0?? ?01? rev. 1.00 117 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi compact type tm operating modes the compact type tm can operate in one of three operating modes, compare match output mode, pwm mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is generated after a compare match occurs from comparator a. the tnpf interrupt request flag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.00 116 ???i? 0?? ?01? rev. 1.00 117 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi counte? va?ue 0 x? ff ccrp ccr? tnon tnp?u tnpol ccrp int . f?ag tnpf ccr? int . f?ag tn?f tm o / p pin time ccrp = 0 ccrp > 0 counte? ove?f?ow ccrp > 0 counte? c?ea?ed by ccrp va?ue pause resume sto? counte? resta?t tncclr = 0 ; tnm [ 1 : 0 ] = 00 out?ut ?in set to initia? leve? low if tnoc = 0 out?ut togg?e with tn?f f?ag note tnio [ 1 : 0 ] = 10 ?ctive high out?ut se?ect he?e tnio [ 1 : 0 ] = 11 togg?e out?ut se?ect out?ut not affected by tn?f f?ag . remains high unti? ?eset by tnon bit out?ut pin reset to initia? va?ue out?ut cont?o??ed by othe? ?in - sha?ed function out?ut inve?ts when tnpol is high compare match output mode C tncclr=0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.00 118 ???i? 0?? ?01? rev. 1.00 119 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi counte? va?ue 0x?ff ccrp ccr? tnon tnp?u tnpol ccrp int. f?ag tnpf ccr? int. f?ag tn?f tm o/p pin time ccr?=0 ccr? = 0 counte? ove?f?ow ccr? > 0 counte? c?ea?ed by ccr? va?ue pause resume sto? counte? resta?t tncclr = 1; tnm [1:0] = 00 out?ut ?in set to initia? leve? low if tnoc=0 out?ut togg?e with tn?f f?ag note tnio [1:0] = 10 ?ctive high out?ut se?ect he?e tnio [1:0] = 11 togg?e out?ut se?ect out?ut not affected by tn?f f?ag. remains high unti? ?eset by tnon bit out?ut pin reset to initia? va?ue out?ut cont?o??ed by othe? ?in-sha?ed function out?ut inve?ts when tnpol is high tnpf not gene?ated no tn?f f?ag gene?ated on ccr? ove?f?ow out?ut does not change compare match output mode C tncclr=1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1
rev. 1.00 118 ???i? 0?? ?01? rev. 1.00 119 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ctm, pwm mode, edge-aligned mode, tndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe?iod 1?8 ?56 ?84 51? 640 768 896 10?4 duty ccr? if f sys =16mhz, tm clock source is f sys /4, ccrp=100b and ccra=128, the ctm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125 khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ctm, pwm mode, edge-aligned mode, tndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe?iod ccr? duty 1?8 ?56 ?84 51? 640 768 896 10?4 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.00 1?0 ???i? 0?? ?01? rev. 1.00 1?1 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi counte? va?ue ccrp ccr? tnon tnp?u tnpol ccrp int. f?ag tnpf ccr? int. f?ag tn?f tm o/p pin (tnoc=1) time counte? c?ea?ed by ccrp pause resume counte? sto? if tnon bit ?ow counte? reset when tnon ?etu?ns high tndpx = 0; tnm [1:0] = 10 pwm duty cyc?e set by ccr? pwm ?esumes o?e?ation out?ut cont?o??ed by othe? ?in-sha?ed function out?ut inve?ts when tnpol = 1 pwm pe?iod set by ccrp tm o/p pin (tnoc=0) pwm mode C tndpx=0 note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.00 1?0 ???i? 0?? ?01? rev. 1.00 1?1 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi counte? va?ue ccrp ccr? tnon tnp?u tnpol ccrp int. f?ag tnpf ccr? int. f?ag tn?f tm o/p pin (tnoc=1) time counte? c?ea?ed by ccr? pause resume counte? sto? if tnon bit ?ow counte? reset when tnon ?etu?ns high tndpx = 1; tnm [1:0] = 10 pwm duty cyc?e set by ccrp pwm ?esumes o?e?ation out?ut cont?o??ed by othe? ?in-sha?ed function out?ut inve?ts when tnpol = 1 pwm pe?iod set by ccr? tm o/p pin (tnoc=0) pwm mode C tndpx=1 note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.00 1?? ???i? 0?? ?01? rev. 1.00 1?? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi standard type tm C stm the standard type tm contains five operating modes, which are compare match output, timer/event counter, capture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external input pin and can drive one or two external output pins. ctm name tm no. tm input pin tm output pin HT66FB540 ht66fb550 ht66fb560 16-bit stm 10-bit stm 0? 1 tck0? tck1 tp0_0? tp0_1 tp1_0? tp1_1 standard tm operation there are two sizes of standard tms, one is 10-bits wide and the other is 16-bits wide. at the core is a 10 or 16-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 3 or 8-bits wide whose value is compared the with highest 3 or 8 bits in the counter while the ccra is the ten or sixteen bits and therefore compares all counter bits. the only way of changing the value of the 10 or 16-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the standard type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
? ? ? ? ?? - ? ? - ?? ? ? ?? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ?? ? ??? ?? ?? ? ? ? standard type tm block diagram standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10 or 16-bit value, while a read/write register pair exists to store the internal 10 or 16-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three or eight ccrp bits.
rev. 1.00 1?? ???i? 0?? ?01? rev. 1.00 1?? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi 16-bit standard tm register list name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm0c0 t0p ?u t0ck? t0ck1 t0ck0 t0on tm0c1 t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0px t0clr tm0dl d7 d6 d5 d4 d? d? d1 d0 tm0dh d15 d14 d1? d1? d11 d10 d9 d8 tm0?l d7 d6 d5 d4 d? d? d1 d0 tm0?h d15 d14 d1? d1? d11 d10 d9 d8 tm0rp d7 d6 d5 d4 d? d? d1 d0 16-bit standard tm register list tm0c0 register C 16-bit stm bit 7 6 5 4 3 2 1 0 name t0p ?u t0ck? t0ck1 t0ck0 t0on r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 t0pau: tm0 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t0ck2, t0ck1, t0ck0: select tm0 counter clock 000: f sys/4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: reserved 110: tck0 rising edge clock 111: tck0 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 t0on: tm0 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t0oc bit, when the t0on bit changes from low to high. bit 2~0 unimplemented, read as "0"
rev. 1.00 1?4 ???i? 0?? ?01? rev. 1.00 1?5 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi tm0c1 register C 16-bit stm bit 7 6 5 4 3 2 1 0 name t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t0m1~t0m0: select tm0 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t0m1 and t0m0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t0io1~t0io0: select tp0_0, tp0_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: force inactive state 01: force active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp0_0, tp0_1 01: input capture at falling edge of tp0_0, tp0_1 10: input capture at falling/rising edge of tp0_0, tp0_1 11: input capture disabled timer/counter mode: unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t0io1 and t0io0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t0oc bit in the tm0c1 register. note that the output level requested by the t0io1 and t0io0 bits must be different from the initial value setup using the t0oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t0on bit from low to high. in the pwm mode, the t0io1 and t0io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the values of the t0io1 and t0io0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t0io1 and t0io0 bits are changed when the tm is running.
rev. 1.00 1?4 ???i? 0?? ?01? rev. 1.00 1?5 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi bit 3 t0oc: tp0_0, tp0_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t0pol: tp0_0, tp0_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp0_0 or tp0_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t0dpx: tm0 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t0cclr: select tm0 counter clear condition 0: tm0 comparator p match 1: tm0 comparator a match this bit is used to select the method which clears the counter. remember that the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t0cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t0cclr bit is not used in the pwm, single pulse or input capture mode. tm0dl register C 16-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm0dl: tm0 counter low byte register bit 7~bit 0 tm0 16-bit counter bit 7~bit 0 tm0dh register C 16-bit stm bit 7 6 5 4 3 2 1 0 name d15 d14 d1? d1? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm0dh: tm0 counter high byte register bit 7~bit 0 tm0 16-bit counter bit 15~bit 8
rev. 1.00 1?6 ???i? 0?? ?01? rev. 1.00 1?7 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi tm0al register C 16-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm0al: tm0 ccra low byte register bit 7~bit 0 tm0 16-bit ccra bit 7~bit 0 tm0ah register C 16-bit stm bit 7 6 5 4 3 2 1 0 name d15 d14 d1? d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm0ah: tm0 ccra high byte register bit 7~bit 0 tm0 16-bit ccra bit 15~bit 8 tm0rp register C 16-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm0rp: tm0 ccrp register bit 7~bit 0 tm0 ccrp 8-bit register, compared with the tm0 counter bit 15~bit 8. comparator p match period 0: 65536 tm0 clocks 1~255: 256(1~255) tm0 clocks these eight bits are used to setup the value on the internal ccrp 8-bit register, which are then compared with the internal counters highest eight bits. the result of this comparison can be selected to clear the internal counter if the t0cclr bit is set to zero. setting the t0cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. 10-bit standard tm register list name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm1c0 t1p ?u t1ck? t1ck1 t1ck0 t1on t1rp? t1rp1 t1rp0 tm1c1 t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1px t1clr tm1dl d7 d6 d5 d4 d? d? d1 d0 tm1dh d9 d8 tm1?l d7 d6 d5 d4 d? d? d1 d0 tm1?h d9 d8 10-bit standard tm register list
rev. 1.00 1?6 ???i? 0?? ?01? rev. 1.00 1?7 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi tm1c0 register bit 7 6 5 4 3 2 1 0 name t1p ?u t1ck? t1ck1 t1ck0 t1on t1rp? t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1pau: tm1 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0: select tm1 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefned 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 t1on: tm1 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0: tmn ccrp 3-bit register, compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counters highest three bits. the result of this comparison can be selected to clear the internal counter if the t1cclr bit is set to zero. setting the t1cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
rev. 1.00 1?8 ???i? 0?? ?01? rev. 1.00 1?9 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi tm1c1 register bit 7 6 5 4 3 2 1 0 name t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1m1~t1m0: select tm1 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1m1 and t1m0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1io1~t1io0: select tp1_0, tp1_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1_0, tp1_1 01: input capture at falling edge of tp1_0, tp1_1 10: input capture at falling/rising edge of tp1_0, tp1_1 11: input capture disabled timer/counter mode: unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1io1 and t1io0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1oc bit in the tm1c1 register. note that the output level requested by the t1io1 and t1io0 bits must be different from the initial value setup using the t1oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1io1 and t1io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the values of the t1io1 and t1io0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1io1 and t1io0 bits are changed when the tm is running.
rev. 1.00 1?8 ???i? 0?? ?01? rev. 1.00 1?9 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi bit 3 t1oc: tp1_0, tp1_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1pol: tp1_0, tp1_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1_0 or tp1_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t1dpx: tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t1cclr: select tm1 counter clear condition 0: tm1 comparator p match 1: tm1 comparator a match this bit is used to select the method which clears the counter. remember that the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm, single pulse or input capture mode. tm1dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dl: tm1 counter low byte register bit 7~bit 0 tmn 10-bit counter bit 7~bit 0 tm1dh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented bit 1~0 tm1dh: tm1 counter high byte register bit 1~bit 0 tmn 10-bit counter bit 9~bit 8
rev. 1.00 1?0 ???i? 0?? ?01? rev. 1.00 1?1 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi tm1al register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1al: tm1 ccra low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0 tm1ah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented bit 1~0 tm1ah: tm1 ccra high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8 standard type tm operating modes the standard type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both tnaf and tnpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. in the compare match output mode, the ccra can not be set to 0. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is generated after a compare match occurs from comparator a. the tnpf interrupt request flag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.00 1?0 ???i? 0?? ?01? rev. 1.00 1?1 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi counte? va?ue 0x?ff ccrp ccr? tnon tnp?u tnpol ccrp int. f?ag tnpf ccr? int. f?ag tn?f tm o/p pin time ccrp=0 ccrp > 0 counte? ove?f?ow ccrp > 0 counte? c?ea?ed by ccrp va?ue pause resume sto? counte? resta?t tncclr = 0; tnm [1:0] = 00 out?ut ?in set to initia? leve? low if tnoc=0 out?ut togg?e with tn?f f?ag note tnio [1:0] = 10 ?ctive high out?ut se?ect he?e tnio [1:0] = 11 togg?e out?ut se?ect out?ut not affected by tn?f f?ag. remains high unti? ?eset by tnon bit out?ut pin reset to initia? va?ue out?ut cont?o??ed by othe? ?in-sha?ed function out?ut inve?ts when tnpol is high compare match output mode C tncclr=0 note: 1. with tncclr=0 a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. n=0, 1
rev. 1.00 1?? ???i? 0?? ?01? rev. 1.00 1?? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi counte? va?ue 0x?ff ccrp ccr? tnon tnp?u tnpol ccrp int. f?ag tnpf ccr? int. f?ag tn?f tm o/p pin time ccr?=0 ccr? = 0 counte? ove?f?ow ccr? > 0 counte? c?ea?ed by ccr? va?ue pause resume sto? counte? resta?t tncclr = 1; tnm [1:0] = 00 out?ut ?in set to initia? leve? low if tnoc=0 out?ut togg?e with tn?f f?ag note tnio [1:0] = 10 ?ctive high out?ut se?ect he?e tnio [1:0] = 11 togg?e out?ut se?ect out?ut not affected by tn?f f?ag. remains high unti? ?eset by tnon bit out?ut pin reset to initia? va?ue out?ut cont?o??ed by othe? ?in-sha?ed function out?ut inve?ts when tnpol is high tnpf not gene?ated no tn?f f?ag gene?ated on ccr? ove?f?ow out?ut does not change compare match output mode C tncclr=1 note: 1. with tncclr=1 a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf fag is not generated when tncclr=1
rev. 1.00 1?? ???i? 0?? ?01? rev. 1.00 1?? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect as the pwm period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. 16-bit stm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 1~255 000b pe?iod ccrp?56 655?6 duty ccr? if f sys =16mhz, tm clock source select f sys /4, ccrp=2 and ccra=128, the stm pwm output frequency=(f sys /4)/(2256)=f sys /2048=7.8125khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 16-bit stm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 1~255 000b pe?iod ccr? duty ccrp x ?56 655?6 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the (ccrp256) except when ccrp value is equal to 000b.
rev. 1.00 1?4 ???i? 0?? ?01? rev. 1.00 1?5 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi 10-bit stm, pwm mode, edge-aligned mode, t1dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe?iod 1?8 ?56 ?84 51? 640 768 896 10?4 duty ccr? if f sys =16mhz, tm clock source select f sys /4, ccrp=100b and ccra=128, the stm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 10-bit stm, pwm mode, edge-aligned mode, t1dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe?iod ccr? duty 1?8 ?56 ?84 51? 640 768 896 10?4 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the ccrp register value. counte? va?ue ccrp ccr? tnon tnp?u tnpol ccrp int. f?ag tnpf ccr? int. f?ag tn?f tm o/p pin (tnoc=1) time counte? c?ea?ed by ccrp pause resume counte? sto? if tnon bit ?ow counte? reset when tnon ?etu?ns high tndpx = 0; tnm [1:0] = 10 pwm duty cyc?e set by ccr? pwm ?esumes o?e?ation out?ut cont?o??ed by othe? ?in-sha?ed function out?ut inve?ts when tnpol = 1 pwm pe?iod set by ccrp tm o/p pin (tnoc=0) pwm mode C tndpx=0 note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.00 1?4 ???i? 0?? ?01? rev. 1.00 1?5 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi counte? va?ue ccrp ccr? tnon tnp?u tnpol ccrp int. f?ag tnpf ccr? int. f?ag tn?f tm o/p pin (tnoc=1) time counte? c?ea?ed by ccr? pause resume counte? sto? if tnon bit ?ow counte? reset when tnon ?etu?ns high tndpx = 1; tnm [1:0] = 10 pwm duty cyc?e set by ccrp pwm ?esumes o?e?ation out?ut cont?o??ed by othe? ?in-sha?ed function out?ut inve?ts when tnpol = 1 pwm pe?iod set by ccr? tm o/p pin (tnoc=0) pwm mode C tndpx=1 note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.00 1?6 ???i? 0?? ?01? rev. 1.00 1?7 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi single pulse mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr and tndpx bits are not used in this mode.

? ? ? ? ? ? ? ? ? ?? single pulse generation
rev. 1.00 1?6 ???i? 0?? ?01? rev. 1.00 1?7 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi counte? va?ue ccrp ccr? tnon tnp?u tnpol ccrp int. f?ag tnpf ccr? int. f?ag tn?f tm o/p pin (tnoc=1) time counte? sto??ed by ccr? pause resume counte? sto?s by softwa?e counte? reset when tnon ?etu?ns high tnm [1:0] = 10 ; tnio [1:0] = 11 pu?se width set by ccr? out?ut inve?ts when tnpol = 1 no ccrp inte??u?ts gene?ated tm o/p pin (tnoc=0) tckn ?in softwa?e t?igge? c?ea?ed by ccr? match tckn ?in t?igge? ?uto. set by tckn ?in softwa?e t?igge? softwa?e c?ea? softwa?e t?igge? softwa?e t?igge? single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit hight 5. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed.
rev. 1.00 1?8 ???i? 0?? ?01? rev. 1.00 1?9 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi capture input mode to select this mode bits tnm1 and tnm0 in the tmnc1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpn_0 or tpn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnio1 and tnio0 bits in the tmnc1 register. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpn_0 or tpn_1 pin the present value in the counter will be latched into the ccra registers and a tm interrupt generated. irrespective of what events occur on the tpn_0 or tpn_1 pin the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overflow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnio1 and tnio0 bits can select the active trigger edge on the tpn_0 or tpn_1 pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpn_0 or tpn_1 pin, however it must be noted that the counter will continue to run. as the tpn_0 or tpn_1 pin is pin shared with other functions, care must be taken if the tm is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr and tndpx bits are not used in this mode.
rev. 1.00 1?8 ???i? 0?? ?01? rev. 1.00 1?9 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi counte? va?ue yy ccrp tnon tnp?u ccrp int. f?ag tnpf ccr? int. f?ag tn?f ccr? va?ue time counte? c?ea?ed by ccrp pause resume counte? reset tnm [1:0] = 01 tm ca?tu?e ?in tpn_x xx counte? sto? tnio [1:0] va?ue xx yy xx yy ?ctive edge ?ctive edge ?ctive edge 00 C rising edge 01 C fa??ing edge 10 C both edges 11 C disab?e ca?tu?e capture input mode note: 1. tnm [1:0]=01 and active edge set by the tnio [1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function C tnoc and tnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.00 140 ???i? 0?? ?01? rev. 1.00 141 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the devices contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. part no. input channels a/d channel select bits input pins HT66FB540 8 ?cs4? ?cs?~?cs0 ?n0~?n7 ht66fb550 ht66fb560 16 ?cs4~?cs0 ?n0~?n15 the accompanying block diagram shows the overall internal structure of the a/d converter, together with its associated registers. a/d converter register description overall operation of the a/d converter is controlled using seven registers. a read only register pair exists to store the adc data 12-bit value. the remaining fve registers are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 ?drl(?drfs=0) d? d? d1 d0 ?drl(?drfs=1) d7 d6 d5 d4 d? d? d1 d0 ?drh(?drfs=0) d11 d10 d9 d8 d7 d6 d5 d4 ?drh(?drfs=1) d11 d10 d9 d8 ?dcr0 st ? rt eocb ?doff ?drfs ?cs? ?cs1 ?cs0 ?dcr1 ?cs4 v1?5en vrefs ?dck? ?dck1 ?dck0 ?cer0 ?ce7 ?ce6 ?ce5 ?ce4 ?ce? ?ce? ?ce1 ?ce0 HT66FB540 a/d converter register list register name bit 7 6 5 4 3 2 1 0 ?drl(?drfs=0) d? d? d1 d0 ?drl(?drfs=1) d7 d6 d5 d4 d? d? d1 d0 ?drh(?drfs=0) d11 d10 d9 d8 d7 d6 d5 d4 ?drh(?drfs=1) d11 d10 d9 d8 ?dcr0 st ? rt eocb ?doff ?drfs ?cs? ?cs? ?cs1 ?cs0 ?dcr1 ?cs4 v1?5en vrefs ?dck? ?dck1 ?dck0 ?cer0 ?ce7 ?ce6 ?ce5 ?ce4 ?ce? ?ce? ?ce1 ?ce0 ?cer1 ?ce15 ?ce14 ?ce1? ?ce1? ? ce11 ?ce10 ?ce9 ?ce8 ht66fb550/ht66fb560 a/d converter register list
rev. 1.00 140 ???i? 0?? ?01? rev. 1.00 141 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi

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? ? ? ? ? ? ? a/d converter structure a/d converter data registers C adrl, adrh as the devices contain an internal 12-bit a/d converter, they require two data registers to store the converted value. these are a high byte register, known as adrh, and a low byte register, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompanying table. d0~d11 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d? d? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d? d? d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, acer0, acer1 to control the function and operation of the a/d converter, fve control registers known as adcr0, adcr1, acer0 and acer1 are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter, the digitised data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs3~acs0 bits in the adcr0 register and acs4 bit is the adcr1 register defne the adc input channel number. as the devices contain only one actual analog to digital converter hardware circuit, each of the individual 8 analog inputs must be routed to the converter. it is the function of the acs4 and acs3~acs0 bits to determine which analog channel input pins or internal 1.25v is actually connected to the internal a/d converter. the acer1~acer0 control registers contain the acer15~acer0 bits which determine which pins on pa7, port b and port c are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corresponding bit high will select the a/d input function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input.
rev. 1.00 14? ???i? 0?? ?01? rev. 1.00 14? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi adcr0 register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name st ? rt eocb ?doff ?drfs ?cs? ?cs1 ?cs0 r/w r/w r r/w r/w r r/w r/w r/w por 0 1 1 0 0 0 0 0 bit 7 start: start the a/d conversion 010: start 01: reset the a/d converter and set eocb to 1 this bit is used to initiate an a/d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb: end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running, the bit will be high. bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter. if the bit is set high then the a/d converter will be switched off reducing the devices power consumption. as the a/d converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 adrfs: adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3 unimplemented bit 2~0 acs2, acs1, acs0: select a/d channel (when acs4 is 0) 000: an0 001: an1 010: an2 011: an3 100: an4 101: an5 110: an6 111: an7 these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the eight a/d inputs must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high then the internal 1.25v will be routed to the a/d converter.
rev. 1.00 14? ???i? 0?? ?01? rev. 1.00 14? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb550/ht66fb560 bit 7 6 5 4 3 2 1 0 name st ? rt eocb ?doff ?drfs ?cs? ?cs? ?cs1 ?cs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 0 bit 7 start: start the a/d conversion 010: start 01: reset the a/d converter and set eocb to 1 this bit is used to initiate an a/d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb: end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running, the bit will be high. bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter. if the bit is set high then the a/d converter will be switched off reducing the devices power consumption. as the a/d converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 adrfs: adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3~0 acs3, acs2, acs1, acs0: select a/d channel (when acs4 is 0) 0000: an0 0001: an1 0010: an2 0011: an3 0100: an4 0101: an5 0110: an6 0111: an7 1000: an8 1001: an9 1010: an10 1011: an11 1100: an12 1101: an13 1110: an14 1111: an15 these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the eight a/d inputs must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high then the internal 1.25v will be routed to the a/d converter.
rev. 1.00 144 ???i? 0?? ?01? rev. 1.00 145 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi adcr1 register bit 7 6 5 4 3 2 1 0 name ?cs4 v1?5en vrefs ?dck? ?dck1 ?dck0 r/w r/w r/w r r/w r r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 acs4: select internal 1.25v bandgap voltage as adc input 0: disable 1: enable this bit enables the1.25v bandgap voltage to be connected to the a/d converter. the v125en bit must frst have been set to enable the bandgap circuit 1.25v voltage to be used by the a/d converter. when the acs4 bit is set high, the bandgap 1.25v voltage will be routed to the a/d converter and the other a/d input channels disconnected. bit 6 v125en: internal 1.25v control 0: disable 1: enable this bit controls the internal bandgap circuit on/off function to the a/d converter. when the bit is set high the 1.25v bandgap voltage can be used as an a/d converter input. if the 1.25v bandgap voltage is not used by the a/d converter and the lvr/lvd function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. when the 1.25v bandgap voltage is switched on for use by the a/d converter, a time t bg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 unimplemented bit 4 vrefs: select adc reference voltage 0: internal adc power 1: vref pin this bit is used to select the reference voltage for the a/d converter. if the bit is high, then the a/d converter reference voltage is supplied on the external vref pin. if the pin is low, then the internal reference is used which is taken from the power supply pin, vdd. bit 3 unimplemented bit 2~0 adck2, adck1, adck0: select adc clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: undefned these three bits are used to select the clock source for the a/d converter.
rev. 1.00 144 ???i? 0?? ?01? rev. 1.00 145 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi acer0 register bit 7 6 5 4 3 2 1 0 name ?ce7 ?ce6 ?ce5 ?ce4 ?ce? ?ce? ?ce1 ?ce0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ace7: defne pa7 is a/d input or not 0: not a/d input 1: a/d input, an7 bit 6 ace6: defne pb6 is a/d input or not 0: not a/d input 1: a/d input, an6 bit 5 ace5: defne pb5 is a/d input or not 0: not a/d input 1: a/d input, an5 bit 4 ace4: defne pb4 is a/d input or not 0: not a/d input 1: a/d input, an4 bit 3 ace3: defne pb3 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ace2: defne pb2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ace1: defne pb1 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 ace0: defne pb0 is a/d input or not 0: not a/d input 1: a/d input, an0
rev. 1.00 146 ???i? 0?? ?01? rev. 1.00 147 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi acer1 register ? ht66fb550/ht66fb560 bit 7 6 5 4 3 2 1 0 name ?ce15 ?ce14 ?ce1? ?ce1? ? ce11 ?ce10 ?ce9 ?ce8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ace15: defne pc7 is a/d input or not 0: not a/d input 1: a/d input, an15 bit 6 ace14: defne pc6 is a/d input or not 0: not a/d input 1: a/d input, an14 bit 5 ace13: defne pc5 is a/d input or not 0: not a/d input 1: a/d input, an13 bit 4 ace12: defne pc4 is a/d input or not 0: not a/d input 1: a/d input, an12 bit 3 ace11: defne pc3 is a/d input or not 0: not a/d input 1: a/d input, an11 bit 2 ace10: defne pc2 is a/d input or not 0: not a/d input 1: a/d input, an10 bit 1 ace9: defne pc1 is a/d input or not 0: not a/d input 1: a/d input, an9 bit 0 ace8: defne pc0 is a/d input or not 0: not a/d input 1: a/d input, an8
rev. 1.00 146 ???i? 0?? ?01? rev. 1.00 147 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi a/d operation the start bit in the adcr0 register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the start bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bit in the adcr0 register is used to indicate when the analog to digital conversion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. although the a/d clock source is determined by the system clocky, f sys , and by bits adck2~adck0, there are some limitations on the maximum a/d clock source speed that can be selected. as the minimum value of permissible a/d clock period, t ad , is 0.5s, care must be taken for system clock frequencies equal to or greater than 4mhz. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to 000. doing so will give a/d clock periods that are less than the minimum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the devices, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t ad ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 1mhz 1s 2s 4s 8s 16s 32s 64s undefned ?mhz 500ns 1s 2s 4s 8s 16s 32s undefned 4mhz ?50ns* 500ns 1s 2s 4s 8s 16s undefned 8mhz 1?5ns* ?50ns* 500ns 1s 2s 4s 8s undefned 1?mhz 8?ns* 167ns* ???ns* 667ns 1.33s 2.67s 5.33s undefned 16mhz 6?ns* 1?5ns* ?50ns* 500ns 1s 2s 4s undefned a/d clock period examples controlling the power on/off function of the a/d converter circuitry is implemented using the adoff bit in the adcr0 register. this bit must be zero to power on the a/d converter. even if no pins are selected for use as a/d inputs by clearing the ace15~ace0 bits in the acer1~acer0 registers, if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref. the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically.
rev. 1.00 148 ???i? 0?? ?01? rev. 1.00 149 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on pa7, port b and port c as well as other functions. the ace15~ace0 bits in the acer1~acer0 registers, determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace15~ace0 bits for its corresponding pin is set high then the pin will be setup to be an a/ d converter input and the original pin functions disabled. in this way, pins can be changed under program control to change their function between a/d inputs and other functions. all pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the pac, pbc, pcc port control registers to enable the a/d input as when the ace15~ace0 bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of v ref . summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4~acs0 bits which are also contained in the adcr1 and adcr0 register. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace15~ace0 bits in the acer1~acer0 registers. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, and the a/d converter interrupt bit, ade, must both be set high to do this. ? step 6 the analog to digital conversion process can now be initialised by setting the start bit in the adcr0 register from low to high and then low again. note that this bit should have been originally cleared to zero. ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted.
rev. 1.00 148 ???i? 0?? ?01? rev. 1.00 149 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16t ad where t ad is equal to the a/d clock period.

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? ? ? - ? ? ? ? ?? - a/d conversion timing programming considerations during microcontroller operations where the a/d converter is not being used, the a/d internal circuitry can be switched off to reduce power consumption, by setting bit adoff high in the adcr0 register. when this happens, the internal a/d converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the devices contain a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb=(v dd or v ref )4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage=a/d output digital value (v dd or v ref )4096 the diagram shows the ideal transfer function between the analog input value and the digitised output value for the a/d converter. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level.
rev. 1.00 150 ???i? 0?? ?01? rev. 1.00 151 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the eocb bit in the adcr0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff clr acer1 mov a,0fh ; setup acer to confgure pins an0~an3 mov acer0,a mov a,00h mov adcr0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr0 register eocb bit to detect end ; of a/d conversion jmp polling_eoc ; continue polling mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : jmp start_conversion ; start next a/d conversion
rev. 1.00 150 ???i? 0?? ?01? rev. 1.00 151 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff clr acer1 mov a,0fh ; setup acer to confgure pins an0~an3 mov acer0,a mov a,00h mov adcr0,a ; enable and connect an0 channel to a/d converter start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag set ade ; enable adc interrupt set emi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defned memory mov a,status mov status_stack,a ; save status to user defned memory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a,acc_stack ; restore acc from user defned memory reti
rev. 1.00 15? ???i? 0?? ?01? rev. 1.00 15? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi comparators two independent analog comparators are contained within these devices. these functions offer fexibility via their register controlled features such as power-down, polarity select, hysteresis etc. in sharing their pins with normal i/o pins the comparators do not waste precious i/o pins if there functions are otherwise unused. comparator comparator operation the devices contain two comparator functions which are used to compare two analog voltages and provide an output based on their difference. full control over the two internal comparators is provided via two control registers, cp0c and cp1c, one assigned to each comparator. the comparator output is recorded via a bit in their respective control register, but can also be transferred out onto a shared i/o pin. additional comparator functions include, output polarity, hysteresis functions and power down control. any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. as the comparator inputs approach their switching level, some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals. this can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator. ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level, however, unavoidable input offsets introduce some uncertainties here. the hysteresis function, if enabled, also increases the switching offset value. comparator registers there are two registers for overall comparator operation, one for each comparator. as corresponding bits in the two registers have identical functions, they following register table applies to both registers. register name bit 7 6 5 4 3 2 1 0 cp0c c0sel c0en c0pol c0out c0os c0hyen cp1c c1sel c1en c1pol c1out c1os c1hyen comparator registers list comparator interrupt each also possesses its own interrupt function. when any one of the changes state, its relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. note that it is the changing state on c0int or c1int which generate an interrupt. if the microcontroller is in the sleep or idle mode and the comparator is enabled, then if the external input lines cause the comparator output to change state, the resulting generated interrupt fag will also generate a wake-up. if it is required to disable a wake- up from occurring, then the interrupt fag should be frst set high before entering the sleep or idle mode.
rev. 1.00 15? ???i? 0?? ?01? rev. 1.00 15? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi programming considerations if the comparator is enabled, it will remain active when the microcontroller enters the sleep or idle mode, however as it will consume a certain amount of power, the user may wish to consider disabling it before the sleep or idle mode is entered. as comparator pins are shared with normal i/o pins the i/o registers for these pins will be read as zero (port control register is "1") or read as port data register value (port control register is "0") if the comparator function is enabled. cp0c register bit 7 6 5 4 3 2 1 0 name c0sel c0en c0pol c0out c0os c0hyen r/w r/w r/w r/w r r/w r/w por 1 0 0 0 0 1 bit 7 c0sel: select comparator pins or i/o pins 0: i/o pin select 1: comparator pin select this is the comparator pin or i/o pin select bit. if the bit is high the comparator will be selected and the two comparator input pins will be enabled. as a result, these two pins will lose their i/o pin functions. any pull-high confguration options associated with the comparator shared pins will also be automatically disconnected. bit 6 c0en: comparator on/off control 0: off 1: on this is the comparator on/off control bit. if the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the devices enter the sleep or idle mode. bit 5 c0pol: comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the c0out bit will refect the non-inverted output condition of the comparator. if the bit is high the comparator c0out bit will be inverted. bit 4 c0out: comparator output bit c0pol=0 0: c0+ < c0- 1: c0+ > c0- c0pol=1 0: c0+ > c0- 1: c0+ < c0- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the c0pol bit. bit 3 c0os: output path select 0: c0x pin 1: internal use this is the comparator output path select control bit. if the bit is set to "0" and the c0sel bit is "1" the comparator output is connected to an external c0x pin. if the bit is set to "1" or the c0sel bit is "0" the comparator output signal is only used internally by the devices allowing the shared comparator output pin to retain its normal i/o operation. bit 2~1 unimplemented, read as "0" bit 0 c0hyen: hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold.
rev. 1.00 154 ???i? 0?? ?01? rev. 1.00 155 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? cp1c register bit 7 6 5 4 3 2 1 0 name c1sel c1en c1pol c1out c1os c1hyen r/w r/w r/w r/w r r/w r/w por 1 0 0 0 0 1 bit 7 c1sel: select comparator pins or i/o pins 0: i/o pin select 1: comparator pin select this is the comparator pin or i/o pin select bit. if the bit is high the comparator will be selected and the two comparator input pins will be enabled. as a result, these two pins will lose their i/o pin functions. any pull-high confguration options associated with the comparator shared pins will also be automatically disconnected. bit 6 c1en: comparator on/off control 0: off 1: on this is the comparator on/off control bit. if the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the devices enter the sleep or idle mode. bit 5 c1pol: comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the c1out bit will refect the non-inverted output condition of the comparator. if the bit is high the comparator c1out bit will be inverted. bit 4 c1out: comparator output bit c1pol=0 0: c1+ < c1- 1: c1+ > c1- c1pol=1 0: c1+ > c1- 1: c1+ < c1- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the c1pol bit. bit 3 c1os: output path select 0: c1x pin 1: internal use this is the comparator output path select control bit. if the bit is set to "0" and the c1sel bit is "1" the comparator output is connected to an external c1x pin. if the bit is set to "1" or the c1sel bit is "0" the comparator output signal is only used internally by the devices allowing the shared comparator output pin to retain its normal i/o operation. bit 2~1 unimplemented, read as "0" bit 0 c1hyen: hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold.
rev. 1.00 154 ???i? 0?? ?01? rev. 1.00 155 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi serial interface module C sim the devices contain a serial interface module, which includes both the four line spi interface and the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim interface pins are pin-shared with other i/o pins therefore the sim interface function must frst be selected by software control. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. these pull-high resistors of the sim pin-shared i/o are selected using pull-high control registers, and also if the sim function is enabled. there is one control register associated with the serial interface control, namely sbsc. this is used to enable the sim wcol bit function, spia wcol bit function and i 2 c debounce selection. the devices provide two kinds of spi function, namely spi and spia, each of them has the corresponding wcol control bits to enable the sim wcol and spia wcol control bits, namely sim_wcol and sa_wcol respectively. in addition, the i2cdb1 and i2cdb0 bits are used to select the i 2 c debounce time. spi interface this spi interface function, which is part of the serial interface module, should not be confused with the other independent spi function, known as spia, which is described in another section of this datasheet. the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the devices can be either master or slave. although the spi interface specifcation can control multiple slave devices from a single master, but these devices provided only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with other functions and with the i 2 c function pins, the spi interface must frst be selected by the correct bits in the simc0 and simc2 registers. after the spi option has been selected, it can also be additionally disabled or enabled using the simen bit in the simc0 register. spi master/slave connection
rev. 1.00 156 ???i? 0?? ?01? rev. 1.00 157 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi

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?? ? ? ? - ? ? ? ? ? ? ?? ? ??? ? ? ? ? spi bolck diagram the spi function in these devices offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge ? wcol bit enabled or disable select the status of the spi interface pins is determined by a number of factors such as whether the devices are in the master or slave mode and upon the condition of certain control bits such as csen and simen.
rev. 1.00 156 ???i? 0?? ?01? rev. 1.00 157 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi spi registers there are four internal registers which control the overall operation of the spi interface. these are the simd data register and three registers simc0, simc2 and sbsc. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim? sim1 sim0 pcken pckp1 pckp0 simen simd d7 d6 d5 d4 d? d? d1 d0 simc? d7 d6 ckpolb ckeg mls csen wcol trf sbsc sim_wcol i?cdb1 i?cdb0 s?_wcol sim registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the devices write data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the devices can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" unknown there are also three control registers for the spi interface, simc0 and simc2 and sbsc. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi function, only by the i 2 c function. register simc0 is used to control the enable/disable function and to set the data transmission clock frequency. although not connected with the spi function, the simc0 register is also used to control the peripheral clock prescaler. register simc2 is used for other control functions such as lsb/msb selection, write collision fag etc. the sim_wcol bit in the sbsc register is used to control the spi wcol function.
rev. 1.00 158 ???i? 0?? ?01? rev. 1.00 159 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi simc0 register bit 7 6 5 4 3 2 1 0 name sim? sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0: sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: non sim function these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from tm0. if the spi slave mode is selected then the clock will be supplied by an external master devices. bit 4 pcken: pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0: select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen: sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will lose their spi or i 2 c function and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be frst initialised by the application program while the relevant i 2 c fags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented
rev. 1.00 158 ???i? 0?? ?01? rev. 1.00 159 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi simc2 register bit 7 6 5 4 3 2 1 0 name d7 d6 ckpolb ckeg mls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 undefned bit this bit can be read or written by the application program. bit 5 ckpolb: determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. bit 4 ckeg: determines spi sck active clock edge type ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is executed otherwise an erroneous clock edge may be generated. the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls: spi data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen: spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low, then the scs pin will be disabled and placed into i/o pin or the other functions. if the bit is high the scs pin will be enabled and used as a select pin. bit 1 wcol: spi write collision fag 0: no collision 1: collision the wcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that using the wcol bit can be disabled or enabled via the sim_wcol bit in the sbsc register. bit 0 trf: spi transmit/receive complete fag 0: data is being transferred 1: spi data transmission is completed the trf bit is the transmit/receive complete fag and is set 1 automatically when an spi data transmission is completed, but must set to 0 by the application program. it can be used to generate an interrupt.
rev. 1.00 160 ???i? 0?? ?01? rev. 1.00 161 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi sbsc register bit 7 6 5 4 3 2 1 0 name sim_wcol i?cdb1 i?cdb0 s?_wcol r/w r/w r r/w r/w r r r r/w por 0 0 0 0 0 0 0 0 bit 7: sim_wcol: sim wcol control bit 0: disable 1: enable bit 6: unimplemented bit 5,4: i2cdb1, i2cdb0 : i 2 c debounce selection bits related to i 2 c function, described elsewhere bit 3~1: unimplemented bit 0: sa_wcol : spia wcol function control 0: disable 1: enable related to spia function, described elsewhere spi communication after the spi interface is enabled by setting the simen bit high, then in the master mode, when data is written to the simd register, transmission/reception will begin simultaneously. when the data transfer is complete, the trf flag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register. the master should output an scs signal to enable the slave devices before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode.
rev. 1.00 160 ???i? 0?? ?01? rev. 1.00 161 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi
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? ? spi master mode timing

? ? ? ? ??? ? - ? ? ?? spi slave mode timing C ckeg=0

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rev. 1.00 16? ???i? 0?? ?01? rev. 1.00 16? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi

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? ? ? ? ? ? - ? ?? ? ? ?? ? ? ?? ?? ? ?? ? ??? ??? ? ?? ? ?? ?? ? spi transfer control flowchart spi bus enable/disable to enable the spi bus, set csen=1 and scs =0, then wait for data to be written into the simd (txrx buffer) register. for the master mode, after data has been written to the simd (txrx buffer) register, then transmission or reception will start automatically. when all the data has been transferred, the trf bit should be set. for the slave mode, when clock pulses are received on sck, data in the txrx buffer will be shifted out or data on sdi will be shifted in. to disable the spi bus, the sck, sdi, sdo and scs will become i/o pins or the other functions.
rev. 1.00 16? ???i? 0?? ?01? rev. 1.00 16? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi spi operation all communication is carried out using the 4-line interface for either master or slave mode. the csen bit in the simc2 register controls the overall function of the spi interface. setting this bit high will enable the spi interface by allowing the scs line to be active, which can then be used to control the spi interface. if the csen bit is low, the spi interface will be disabled and the scs line will be an i/o pin or the other functions and can therefore not be used for control of the spi interface. if the csen bit and the simen bit in the simc0 are set high, this will place the sdi line in a foating condition and the sdo line high. if in master mode the sck line will be either high or low depending upon the clock polarity selection bit ckpolb in the simc2 register. if in slave mode the sck line will be in a foating condition. if the simen bit is low, then the bus will be disabled and scs , sdi, sdo and sck will all become i/o pins or the other functions. in the master mode the master will always generate the clock signal. the clock and data transmission will be initiated after data has been written into the simd register. in the slave mode, the clock signal will be received from an external master devices for both data transmission and reception. the following sequences show the order to be followed for data transfer in both master and slave mode: master mode: ? step 1 select the spi master mode and clock source using the sim2~sim0 bits in the simc0 control register ? step 2 setup the csen bit and setup the mls bit to choose if the data is msb or lsb frst, this setting must be the same with the slave devices. ? step 3 setup the simen bit in the simc0 control register to enable the spi interface. ? step 4 for write operations: write the data to the simd register, which will actually place the data into the txrx buffer. then use the sck and scs lines to output the data. after this, go to step5. for read operations: the data transferred in on the sdi line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the simd register. ? step 5 check the wcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the trf bit or wait for a spi serial bus interrupt. ? step 7 read data from the simd register. ? step 8 clear trf. ? step 9 go to step 4.
rev. 1.00 164 ???i? 0?? ?01? rev. 1.00 165 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi slave mode: ? step 1 select the spi slave mode using the sim2~sim0 bits in the simc0 control register ? step 2 setup the csen bit and setup the mls bit to choose if the data is msb or lsb frst, this setting must be the same with the master devices. ? step 3 setup the simen bit in the simc0 control register to enable the spi interface. ? step 4 for write operations: write the data to the simd register, which will actually place the data into the txrx buffer. then wait for the master clock sck and scs signal. after this, go to step5. for read operations: the data transferred in on the sdi line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the simd register. ? step 5 check the wcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the trf bit or wait for a spi serial bus interrupt. ? step 7 read data from the simd register. ? step 8 clear trf. ? step 9 go to step 4. error detection the wcol bit in the simc2 register is provided to indicate errors during data transfer. the bit is set by the spi serial interface but must be cleared by the application program. this bit indicates a data collision has occurred which happens if a write to the simd register takes place during a data transfer operation and will prevent the write operation from continuing. the overall function of the wcol bit can be disabled or enabled by the sim_wcol bit in the sbsc register. . i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data transfer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master slave bus connection
rev. 1.00 164 ???i? 0?? ?01? rev. 1.00 165 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. for these devices, which only operate in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. the debounce time of the i 2 c interface can be determined by the i2cdb1 and i2cdb0 bits in the sbsc register. this uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 1 or 2 system clocks.
i 2 c registers there are three control registers associated with the i 2 c bus, simc0, simc1 and sbsc, one address register sima and one data register, simd. the simd register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the microcontroller can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. the i2cdb0 and i2cdb1 in the sbsc register are used to select the i 2 c debounce time. register name bit 7 6 5 4 3 2 1 0 simc0 sim? sim1 sim0 pcken pckp1 pckp0 simen simc1 hcf h?ns hbb htx tx?k srw i?mwu rx?k simd d7 d6 d5 d4 d? d? d1 d0 sim? iic?6 iic?5 iic?4 iic?? iic?? iic?1 iic?0 d0 sbsc sim_wcol i?cdb1 i?cdb0 s?_wcol i 2 c registers list
rev. 1.00 166 ???i? 0?? ?01? rev. 1.00 167 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi simc0 register bit 7 6 5 4 3 2 1 0 name sim? sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0: sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: non sim function these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken: pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0: select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen: sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. if the sim is confgured to operate as an spi interface via sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be frst initialised by the application program while the relevant i 2 c fags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented
rev. 1.00 166 ???i? 0?? ?01? rev. 1.00 167 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi simc1 register bit 7 6 5 4 3 2 1 0 name hcf h??s hbb htx tx?k srw i?mwu rx?k r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf: i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas: i 2 c bus address match fag 0: not address match 1: address match the hass fag is the address match fag. this fag is used to determine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb: i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb flag is the i 2 c busy flag. this flag will be 1 when the i 2 c bus is busy which will occur when a start signal is detected. the fag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 htx: select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak: i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to 0 before further data is received. bit 2 srw: i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the srw flag is the i 2 c slave read/write flag. this flag determines whether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the srw fag to determine whether it should be in transmit mode or receive mode. if the srw fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the srw flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu: i 2 c address match wake-up control 0: disable 1: enable this bit should be set to 1 to enable i 2 c address match wake up from sleep or idle mode.
rev. 1.00 168 ???i? 0?? ?01? rev. 1.00 169 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi bit 0 rxak: i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave does not receive acknowledge fag the rxak flag is the receiver acknowledge flag. when the rxak flag is 0, it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receiver wishes to receive the next byte. the slave transmitter will therefore continue sending out data until the rxak fag is 1. when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the devices write data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the devices can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" unknown sima register bit 7 6 5 4 3 2 1 0 name iic?6 iic?5 iic?4 iic?? iic?? iic?1 iic?0 r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x "x" unknown bit 7~1 iica6~iica0: i 2 c slave address iica6~iica0 is the i 2 c slave address bit 6~bit 0. the sima register is also used by the spi interface but has the name simc2. the sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~1 of the sima register define the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register, the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 undefned bit this bit can be read or written by user software program.
rev. 1.00 168 ???i? 0?? ?01? rev. 1.00 169 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi sbsc register bit 7 6 5 4 3 2 1 0 name sim_wcol i?cdb1 i?cdb0 s?_wcol r/w r/w r r/w r/w r r r r/w por 0 0 0 0 0 0 0 0 bit 7 sim_wcol : sim wcol control bit related to spi, described elsewhere. bit 6 unimplemented bit 5, 4 i2cdb1, i2cdb0: i2c debounce selection bits 00: no debounce (default) 01: 1 system clock debounce 10, 11: 2 system clocks debounce bit 3~1 unimplemented bit 0 sa_wcol: spia wcol function control related to spia, described elsewhere.

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rev. 1.00 170 ???i? 0?? ?01? rev. 1.00 171 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi i 2 c bus communication communication on the i 2 c bus requires four separate steps, a start signal, a slave device address transmission, a data transmission and finally a stop signal. when a start signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: ? step 1 set the sim2~sim0 and simen bits in the simc0 register to 1 to enable the i 2 c bus. ? step 2 write the slave address of the device to the i 2 c bus address register sima. ? step 3 set the sime and sim muti-function interrupt enable bit of the interrupt control register to enable the sim interrupt and multi-function interrupt.

? ? ? ? ? ? - ? ? ? ? ? ?? ? ? ? ? ? - i 2 c bus initialisation flow chart
rev. 1.00 170 ???i? 0?? ?01? rev. 1.00 171 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi i 2 c bus start signal the start signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this start signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a start condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, defnes the read/write status and will be saved to the srw bit of the simc1 register. the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haas bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. when a slave address is matched, the devices must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c bus read/write signal the srw bit in the simc1 register defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver. if the srw fag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw fag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the srw fag to determine if it is to be a transmitter or a receiver. if the srw fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to 1. if the srw fag is low, then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to 0.
rev. 1.00 17? ???i? 0?? ?01? rev. 1.00 17? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb frst and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level 0, before it can receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter, the slave device must frst write the data to be transmitted into the simd register. if setup as a receiver, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmitter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master.
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- ? ? i 2 c communication timing diagram note: *when a slave address is matched, the devices must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line.
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i 2 c bus isr fow chart i 2 c time out function the i 2 c interface provides a time-out scheme to prevent a locked situation which might take place by an unexpected clock timing generated by a niose input signal. when the i 2 c interface has been locked for a period of time, the i 2 c hardware and the register, simc1, will be initialized automatically and the i2ctof bit in the i2ctoc register will be set high. the time out function eable/disable and the time-out period are managed by the i2ctoc register.
rev. 1.00 174 ???i? 0?? ?01? rev. 1.00 175 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi i 2 c time out operation the time-out counter will start counting when the i 2 c interface received the start bit and address match. after that the counter will be cleared on each falling edge of the scl pin. if the time counter is larger than the selected time-out time, then the anti-locked protection scheme will take place and the time-out counter will be stopped by hardware automatically, the i2ctof bit will be set high and an i 2 c interrupt will also take place. note that this scheme can also be stopped when the i 2 c received the stop bit. there are several time-out periods can be selected by the i2ctos0~i2ctos5 bits in the i2ctoc register. i2ctoc register bit 7 6 5 4 3 2 1 0 name i? ctoen i? ctof i? ctos5 i? ctos4 i? ctos? i? ctos? i? ctos1 i? ctos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 i2ctoen: i 2 c time out function control bit 0: disable 1: enable bit 6 i2ctof: i 2 c time out indication bit 0: not occurred 1: occurred bit 5~0 i2ctos5~i2ctos0: i 2 c time out time period select the i 2 c time out clock is provided by the f sub /32. the time out time period can be calculated from the accompanying equation ([i2ctos5: i2ctos0]+1)(32/f sub ).
rev. 1.00 174 ???i? 0?? ?01? rev. 1.00 175 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi serial interface C spia the devices contain an independent spi function. it is important not to confuse this independent spi function with the additional one contained within the combined sim function, which is described in another section of this datasheet. this independent spi function will carry the name spia to distinguish it from the other one in the sim. the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either master or slave. although the spia interface specifcation can control multiple slave devices from a single master, however these devices are provided with only one scsa pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pins to select the slave devices. spia interface operation the spia interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdia, sdoa, scka and scsa . pins sdia and sdoa are the serial data input and serial data output lines, scka is the serial clock line and scsa is the slave select line. as the spia interface pins are pin-shared with normal i/o pins, the spia interface must frst be enabled by setting the correct bits in the spiac0 and spiac1 registers. the spia can be disabled or enabled using the spiaen bit in the spiac0 register. communication between devices connected to the spia interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. the master also controls the clock signal. as the device only contains a single scsa pin only one slave device can be utilized. the scsa pin is controlled by the application program, set the sacsen bit to 1 to enable the scsa pin function and clear the sacsen bit to 0 to place the scsa pin into a foating state. spia master/slave connection
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?? ? ? ? - ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? spia block diagram the spia function in these devices offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge ? sawcol bit enabled or disable select the status of the spia interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as sacsen and spiaen. there are several configuration options associated with the spia interface. one of these is to enable the spia function which selects the spia pins rather than normal i/o pins. note that if the configuration option does not select the spia function then the spiaen bit in the spiac0 register will have no effect. another two spia confguration options determine if the sacsen and sawcol bits are to be used. spia registers there are four internal registers which control the overall operation of the spia interface. these are the spiad data register and three registers spiac0, spiac1 and sbsc. the sa_wcol bit in the sbsc register is used to control the spia wcol function. register name bit 7 6 5 4 3 2 1 0 spi?c0 s?spi? s?spi1 s?spi0 spi?en spi?c1 s?ckpol s?ckeg s?mls s?csen s? wcol s? trf spi?d d7 d6 d5 d4 d? d? d1 d0 sbsc sim_wcol i?cdb1 i?cdb0 s?_wcol spia registers list the spiad register is used to store the data being transmitted and received. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the spiad register. after the data is received from the spi bus, the device can read it from the spiad register. any transmission or reception of data from the spi bus must be made via the spiad register.
rev. 1.00 176 ???i? 0?? ?01? rev. 1.00 177 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi spiad register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown there are also three control registers for the spia interface, spiac0, spiac1 and sbsc. register spiac0 is used to control the enable/disable function and to set the data transmission clock frequency. register spiac1 is used for other control functions such as lsb/msb selection, write collision fag etc. spiac0 register bit 7 6 5 4 3 2 1 0 name s?spi? s?spi1 s?spi0 spi?en r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 0 bit 7~5 saspi2~saspi0: master/slave clock select 000 : spia master, f sys /4 001 : spia master, f sys /16 010 : spia master, f sys /64 011 : spia master, f tbc 100 : spia master, tm0 ccrp match frequency/2 (pfd) 101 : spia slave 110: unimplemented 111: unimplemented these bits are used to control the spi master/slave selection and the spia master clock frequency. the spia clock is a function of the system clock but can also be chosen to be sourced from tm0. if the spia slave mode is selected then the clock will be supplied by an external master device. bit 4~2 unimplemented, read as 0 bit 1 spiaen: spia enable or disable 0: disable 1: enable the bit is the overall on/off control for the sima interface. when the spiaen bit is cleared to zero to disable the spia interface, the sdia, sdoa, scka and scsa lines will lose their spi function and the spia operating current will be reduced to a minimum value. when the bit is high the spia interface is enabled. bit 0 unimplemented, read as 0
rev. 1.00 178 ???i? 0?? ?01? rev. 1.00 179 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi spiac1 register bit 7 6 5 4 3 2 1 0 name s?ckpol s?ckeg s?mls s?csen s? wcol s? trf r/w r r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0. this bit can be read or written by user software program. bit 5 sackpol: determines the base condition of the clock line 0: scka line will be high when the clock is inactive 1: scka line will be low when the clock is inactive the sackpol bit determines the base condition of the clock line, if the bit is high, then the scka line will be low when the clock is inactive. when the sackpol bit is low, then the scka line will be high when the clock is inactive. bit 4 sackeg: determines the spia scka active clock edge type sackpol=0 0: scka has high base level with data capture on scka rising edge 1: scka has high base level with data capture on scka falling edge sackpol=1 0: scka has low base level with data capture on scka falling edge 1: scka has low base level with data capture on scka rising edge the sackeg and sackpol bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before a data transfer is executed otherwise an erroneous clock edge may be generated. the sackpol bit determines the base condition of the clock line, if the bit is high, then the scka line will be low when the clock is inactive. when the sackpol bit is low, then the scka line will be high when the clock is inactive. the sackeg bit determines active clock edge type which depends upon the condition of the sackpol bit. bit 3 samls: msb/lsb first bit 0: lsb shift frst 1: msb shift frst this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 sacsen: select signal enable/disable bit 0: disable, other functions 1: enable the sacsen bit is used as an enable/disable for the scsa pin. if this bit is low, then the scsa pin will be disabled and placed into other functions. if the bit is high the scsa pin will be enabled and used as a select pin. bit 1 sawcol: write collision bit 0: collision free 1: collision detected the sawcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the spiad register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that this function can be disabled or enabled via the sa_wcol bit in the sbsc register. bit 0 satrf: transmit/receive flag 0: not complete 1: transmission/reception complete the satrf bit is the transmit/receive complete flag and is set 1 automatically when an spia data transmission is completed, but must set to zero by the application program. it can be used to generate an interrupt.
rev. 1.00 178 ???i? 0?? ?01? rev. 1.00 179 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi sbsc register bit 7 6 5 4 3 2 1 0 name sim_wcol i?cdb1 i?cdb0 s?_wcol r/w r/w r r/w r/w r r r r/w por 0 0 0 0 0 0 0 0 bit 7: sim_wcol: sim wcol control bit related to spi, described elsewhere. bit 6: unimplemented bit 5, 4: i2cdb1, i2cdb0: i 2 c debounce selection bits related to i 2 c, described elsewhere. bit 3~1: unimplemented bit 0: sa_wcol: spia wcol function control 0: disable 1: enable spia communication after the spia interface is enabled by setting the spiaen bit high, then in the master mode, when data is written to the spiad register, transmission/reception will begin simultaneously. when the data transfer is complete, the satrf fag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the spiad register will be transmitted and any data on the sdia pin will be shifted into the spiad register. the master should output an scsa signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scsa signal depending upon the confgurations of the sackpol bit and sackeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the sackpol and sackeg bits. the spia will continue to function even in the idle mode.
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? ? ? ??? ? ? - ? ? spia slave mode timing C sackeg=0
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? ? ? ? ? ? ? ? spia slave mode timing C sackeg=1
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? ? ? ? - ? ? ? ? ?? ? ? ?? ?? ? ???? ??? ??? ? ?? ?? ?? ? ? spi transfer control flowchart spia bus enable/disable to enable the spia bus, set sacsen=1 and scsa =0, then wait for data to be written into the spiad (txrx buffer) register. for the master mode, after data has been written to the spiad (txrx buffer) register, then transmission or reception will start automatically. when all the data has been transferred the satrf bit should be set. for the slave mode, when clock pulses are received on scka, data in the txrx buffer will be shifted out or data on sdia will be shifted in. to disable the spia bus scka, sdia, sdoa, scsa will become i/o pins or the other functions.
rev. 1.00 18? ???i? 0?? ?01? rev. 1.00 18? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi spia operation all communication is carried out using the 4-line interface for either master or slave mode. the sacsen bit in the spiac1 register controls the overall function of the spia interface. setting this bit high will enable the spia interface by allowing the scsa line to be active, which can then be used to control the spia interface. if the sacsen bit is low, the spia interface will be disabled and the scsa line will be an i/o pin or the other functions and can therefore not be used for control of the spia interface. if the sacsen bit and the spiaen bit in the spiac0 register are set high, this will place the sdia line in a foating condition and the sdoa line high. if in master mode the scka line will be either high or low depending upon the clock polarity selection bit sackpolb in the spiac1 register. if in slave mode the scka line will be in a foating condition. if spiaen is low then the bus will be disabled and scsa , sdia, sdoa and scka will all become i/o pins or the other functions. in the master mode the master will always generate the clock signal. the clock and data transmission will be initiated after data has been written into the spiad register. in the slave mode, the clock signal will be received from an external master device for both data transmission and reception. the following sequences show the order to be followed for data transfer in both master and slave mode. master mode: ? step 1 select the clock source and master mode using the saspi2~saspi0 bits in the spiac0 control register. ? step 2 setup the sacsen bit and setup the samls bit to choose if the data is msb or lsb frst, this must be same as the slave device. ? step 3 setup the spiaen bit in the spiac0 control register to enable the spia interface. ? step 4 for write operations: write the data to the spiad register, which will actually place the data into the txrx buffer. then use the scka and scsa lines to output the data. after this go to step 5. for read operations: the data transferred in on the sdia line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the spiad register. ? step 5 check the sawcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the satrf bit or wait for a spia serial bus interrupt. ? step 7 read data from the spiad register. ? step 8 clear satrf. ? step 9 go to step 4.
rev. 1.00 18? ???i? 0?? ?01? rev. 1.00 18? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi slave mode: ? step 1 select the spi slave mode using the saspi2~saspi0 bits in the spiac0 control register. ? step 2 setup the sacsen bit and setup the samls bit to choose if the data is msb or lsb frst, this setting must be the same with the master device. ? step 3 setup the spiaen bit in the spiac0 control register to enable the spia interface. ? step 4 for write operations: write the data to the spiad register, which will actually place the data into the txrx buffer. then wait for the master clock scka and scsa signal. after this, go to step 5. for read operations: the data transferred in on the sdia line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the spiad register. ? step 5 check the sawcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the satrf bit or wait for a spia serial bus interrupt. ? step 7 read data from the spiad register. ? step 8 clear satrf. ? step 9 go to step 4. error detection the sawcol bit in the spiac register is provided to indicate errors during data transfer. the bit is set by the spia serial interface but must be cleared by the application program. this bit indicates a data collision has occurred which happens if a write to the spiad register takes place during a data transfer operation and will prevent the write operation from continuing. the overall function of the sawcol bit can be disabled or enabled by the sa_wcol bit in the sbsc register.
rev. 1.00 184 ???i? 0?? ?01? rev. 1.00 185 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pck, is shared with i/o line, the required pin function is chosen via pcken in the simc0 register. the peripheral clock function is controlled using the simc0 register. the clock source for the peripheral clock output can originate from either the tm0 ccrp match frequency/2 or a divided ratio of the internal f sys clock. the pcken bit in the simc0 register is the overall on/off control, setting pcken bit to "1" enables the peripheral clock, setting pcken bit to "0" disables it. the required division ratio of the system clock is selected using the pckp1 and pckp0 bits in the same register. if the device enters the sleep mode this will disable the peripheral clock output. simc0 register bit 7 6 5 4 3 2 1 0 name sim? sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0: sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: non sim function these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken: pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0: select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen: sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. note that when the simen bit changes from low to high the contents of the spi control registers will be in an unknown condition and should therefore be frst initialised by the application program. bit 0 unimplemented
rev. 1.00 184 ???i? 0?? ?01? rev. 1.00 185 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupts are generated by the action of the external int0~int1 and pint pins, while the internal interrupts are generated by various internal functions such as the tms, comparators,time base, lvd, sim , spi , usb, and the a/d converter. interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory, as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the frst is the intc0~intc3 registers which setup the primary interrupts, the second is the mfi0~mfi2 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes g?oba? emi com?a?ato? cpne cpnf n=0 o? 1 intn pin intne intnf n=0 o? 1 ?/d conve?te? ?de ?df mu?ti-function mfne mfnf n=0~4 time base tbne tbnf n=0 o? 1 sim sime simf spi? spi?e spi?f lvd lve lvf tm tnpe tnpf n=0~? tn?e tn?f usb usbe usbf interrupt register bit naming conventions interrupt register contents name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 usbf int1f int0f usbe int1e int0e emi intc1 mf1f mf0f cp1f cp0f mf1e mf0e cp1e cp0e intc? spi?f simf mf?f mf?f spi?e sime mf?e mf?e intc? mf4f tb1f tb0f mf4e tb1e tb0e mfi0 t1?f t1pf t0?f t0pf t1?e t1pe t0?e t0pe mfi1 t??f t?pf t??f t?pf t??e t?pe t??e t?pe mfi? ?df lvf ?de lve
rev. 1.00 186 ???i? 0?? ?01? rev. 1.00 187 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi integ register bit 7 6 5 4 3 2 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r r r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 unimplemented, read as "0 bit 3~2 int1s1, int1s0: interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1, int0s0: interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges intc0 register bit 7 6 5 4 3 2 1 0 name usbf int1f int0f usbe int1e int0e emi r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0 bit 6 usbf: usb interrupt request flag 0: no request 1: interrupt request bit 5 int1f: int1 interrupt request fag 0: no request 1: interrupt request bit 4 int0f: int0 interrupt request fag 0: no request 1: interrupt request bit 3 usbe: usb interrupt control 0: disable 1: enable bit 2 int1e: int1 interrupt control 0: disable 1: enable bit 1 int0e: int0 interrupt control 0: disable 1: enable bit 0 emi: global interrupt control 0: disable 1: enable
rev. 1.00 186 ???i? 0?? ?01? rev. 1.00 187 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi intc1 register bit 7 6 5 4 3 2 1 0 name mf1f mf0f cp1f cp0f mf1e mf0e cp1e cp0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf1f: multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 6 mf0f: multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 5 cp1f: comparator 1 interrupt request flag 0: no request 1: interrupt request bit 4 cp0f: comparator 0 interrupt request flag 0: no request 1: interrupt request bit 3 mf1e: multi-function interrupt 1 interrupt control 0: disable 1: enable bit 2 mf0e: multi-function interrupt 0 interrupt control 0: disable 1: enable bit 1 cp1e: comparator 1 interrupt control 0: disable 1: enable bit 0 cp0e: comparator 0 interrupt control 0: disable 1: enable
rev. 1.00 188 ???i? 0?? ?01? rev. 1.00 189 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi intc2 register bit 7 6 5 4 3 2 1 0 name spi?f simf mf?f mf?f spi?e sime mf?e mf?e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 spiaf: spia interrupt request fag 0: no request 1: interrupt request bit 6 simf: sim interrupt request fag 0: no request 1: interrupt request bit 5 mf3f: multi-function interrupt 3 request flag 0: no request 1: interrupt request bit 4 mf2f: multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 3 spiae: spia interrupt control 0: disable 1: enable bit 2 sime: sim interrupt control 0: disable 1: enable bit 1 mf3e: multi-function interrupt 3 control 0: disable 1: enable bit 0 mf2e: multi-function interrupt 2 control 0: disable 1: enable
rev. 1.00 188 ???i? 0?? ?01? rev. 1.00 189 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi intc3 register bit 7 6 5 4 3 2 1 0 name mf4f tb1f tb0f mf4e tb1e tb0e r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented bit 6 mf4f: multi-function interrupt 4 request fag 0: inactive 1: active bit 5 tb1f: time base 1 interrupt request flag 0: inactive 1: active bit 4 tb0f: time base 0 interrupt request flag 0: inactive 1: active bit 3 unimplemented bit 2 mf4e: multi-function interrupt 4 control 0: no request 1: interrupt request bit 1 tb1e: time base 1 interrupt control 0: disable 1: enable bit 0 tb0e: time base 0 interrupt control 0: disable 1: enable
rev. 1.00 190 ???i? 0?? ?01? rev. 1.00 191 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi mfi0 register bit 7 6 5 4 3 2 1 0 name t1?f t1pf t0?f t0pf t1?e t1pe t0?e t0pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1af: tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t1pf: tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 t0af: tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf: tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 t1ae: tm1 comparator a match interrupt control 0: disable 1: enable bit 2 t1pe: tm1 comparator p match interrupt control 0: disable 1: enable bit 1 t0ae: tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe: tm0 comparator p match interrupt control 0: disable 1: enable
rev. 1.00 190 ???i? 0?? ?01? rev. 1.00 191 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi mfi1 register bit 7 6 5 4 3 2 1 0 name t??f t?pf t??f t?pf t??e t?pe t??e t?pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t3af: tm3 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t3pf: tm3 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 t2af: tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t2pf: tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 t3ae: tm3 comparator a match interrupt control 0: disable 1: enable bit 2 t3pe: tm3 comparator p match interrupt control 0: disable 1: enable bit 1 t2ae: tm2 comparator a match interrupt control 0: disable 1: enable bit 0 t2pe: tm2 comparator p match interrupt control 0: disable 1: enable
rev. 1.00 19? ???i? 0?? ?01? rev. 1.00 19? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi mfi2 register bit 7 6 5 4 3 2 1 0 name ?df lvf ?de lve r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 unimplemented bit 6 adf: adc converter interrupt request fag 0: no request 1: interrupt request bit 5 unimplemented bit 4 lvf: lvd interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented bit 2 ade: adc converter interrupt control 0: disable 1: enable bit 1 unimplemented bit 0 lve: lvd interrupt control 0: disable 1: enable interrupt operation when the conditions for an interrupt event occur, such as a tm compare p, compare a or compare b match or a/d conversion completion etc, the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request fag will still be recorded.
rev. 1.00 19? ???i? 0?? ?01? rev. 1.00 19? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied. all of the interrupt request fags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. 18h request f ? ags enab ? e bits inte ?? u?t name xxf legend request f ? ag C no auto ? eset in isr xxf request f ? ag C auto ? eset in isr xxe enab ? e bit emi auto disab ? ed in isr t1pf tm1 p t1pe t ?? f tm ? ? t ?? e t ? pf tm ? p t ? pe t0 ?f tm0 ? t0 ?e t0pf tm0 p t0pe emi mf0f m. funct . 0 mf0e 1ch emi mf1f m. funct . 1 mf1e t ? pf tm ? p t ? pe t ?? f tm ? ? t ?? e low p ? io ? ity high vector 04h 08h 10h 14h emi emi emi emi int0f int0 pin int0e int1f int1 pin int1e cp0f com ? . 0 cp0e cp1f com ? . 1 cp1e request flags enable bits master enable interrupt name inte ?? u? ts contained within mu? ti - function inte ?? u? ts t1 ?f tm1 ? t1 ?e ?0h emi mf ?f m. funct . ? mf ?e emi tb0f time base 0 tb0e ?0h emi tb1f time base 1 tb1e ?4h ? df ? /d ? de ?4h emi mf ?f m. funct . ? mf ?e ?8h emi simf sim sime ? ch emi spi ?f spi ? spi ?e 0ch emi usbf usb usbe ?8h emi mf4f m. funct . 4 mf4e lvf lvd lve 18h request f ? ags enab ? e bits inte ?? u?t name xxf legend request f ? ag C no auto ? eset in isr xxf request f ? ag C auto ? eset in isr xxe enab ? e bit xxf legend request f ? ag C no auto ? eset in isr xxf request f ? ag C auto ? eset in isr xxe enab ? e bit emi auto disab ? ed in isr emi auto disab ? ed in isr t1pf tm1 p t1pe t ?? f tm ? ? t ?? e t ? pf tm ? p t ? pe t0 ?f tm0 ? t0 ?e t0pf tm0 p t0pe emi mf0f m. funct . 0 mf0e 1ch emi mf1f m. funct . 1 mf1e t ? pf tm ? p t ? pe t ?? f tm ? ? t ?? e t ?? f tm ? ? t ?? e low p ? io ? ity high vector 04h 08h 10h 14h emi emi emi emi int0f int0 pin int0e int1f int1 pin int1e cp0f com ? . 0 cp0e cp1f com ? . 1 cp1e request flags enable bits master enable interrupt name inte ?? u? ts contained within mu? ti - function inte ?? u? ts t1 ?f tm1 ? t1 ?e t1 ?f tm1 ? t1 ?e ?0h emi mf ?f m. funct . ? mf ?e emi tb0f time base 0 tb0e ?0h emi tb1f time base 1 tb1e ?4h ? df ? /d ? de ?4h emi mf ?f m. funct . ? mf ?e ?4h emi mf ?f m. funct . ? mf ?e ?4h emi mf ?f m. funct . ? mf ?f m. funct . ? mf ?e ?8h emi simf sim sime ?8h emi simf sim simf sim sime ? ch emi spi ?f spi ? spi ?e 0ch emi usbf usb usbe ?8h emi mf4f m. funct . 4 mf4e ?8h emi mf4f m. funct . 4 mf4e ?8h emi mf4f m. funct . 4 mf4f m. funct . 4 mf4e lvf lvd lve
rev. 1.00 194 ???i? 0?? ?01? rev. 1.00 195 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi external interrupt the external interrupts are controlled by signal transitions on the pins int0 and int1. an external interrupt request will take place when the external interrupt request fags, int0f, int1f, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e, int1e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external interrupt request fags, int0f, int1f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. comparator interrupt the comparator interrupts are controlled by the two internal comparators. a comparator interrupt request will take place when the comparator interrupt request flags, cp0f or cp1f, are set, a situation that will occur when the comparator output changes state. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and comparator interrupt enable bits, cp0e and cp1e, must frst be set. when the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. when the interrupt is serviced, the comparator interrupt request fags, cp0f, cp1f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. usb interrupt a usb interrupt request will take place when the usb interrupt request flags, usbf, is set, a situation that will occur when an endpoint is accessed. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and usb interrupt enable bit, usbe, must frst be set. when the interrupt is enabled, the stack is not full and an endpoint is accessed, a subroutine call to the usb interrupt vector, will take place. when the interrupt is serviced, the usb interrupt request fag, usbf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts.
rev. 1.00 194 ???i? 0?? ?01? rev. 1.00 195 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi multi-function interrupt within these devices there are up to fve multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts, sim interrupt, spia interrupt, adc interrupt and lvd interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, mf0f~mf4f are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request flag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt fags will be automatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupts, adc interrupt and lvd interrupt will not be automatically reset and must be manually reset by the application program. a/d converter interrupt the a/d converter interrupt is contained within the multi-function interrupt. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf, is set, which occurs when the a/d conversion process fnishes. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the multi-function interrupt vector, will take place. when the a/d converter interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the adf fag will not be automatically cleared, it has to be cleared by the application program. time base interrupts the function of the time base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. to allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the time base overfows, a subroutine call to their respective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f, will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the time base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the time base interrupt period, can originate from several different sources, as shown in the system operating mode section.
rev. 1.00 196 ???i? 0?? ?01? rev. 1.00 197 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 lxtlp tb0? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 0 1 1 1 bit 7 tbon: tb0 and tb1 control 0: disable 1: enable bit 6 tbck: select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb11~tb10: select time base 1 time-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3 lxtlp: lxt low power control 0: disable 1: enable bit 2~0 tb02~tb00: select time base 0 time-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb

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time base interrupts serial interface module interrupts C sim interrupt the serial interface module interrupt, also known as the sim interrupt, will take place when the sim interrupt request flag, simf, is set, which occurs when a byte of data has been received or transmitted by the sim interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, must frst be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the sim interface, a subroutine call to the respective interrupt vector, will take place. when the interrupt is serviced, the serial interface interrupt flag, simf, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.00 196 ???i? 0?? ?01? rev. 1.00 197 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi serial peripheral interface interrupt C spia interrupt the serial peripheral interface interrupt, also known as the spia interrupt, will take place when the spia interrupt request fag, spiaf, is set, which occurs when a byte of data has been received or transmitted by the spia interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, spiae, must frst be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the spia interface, a subroutine call to the respective interrupt vector, will take place. when the interrupt is serviced, the serial interface interrupt fag, spiaf, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. lvd interrupt the low voltage detector interrupt is contained within the multi-function interrupt. an lvd interrupt request will take place when the lvd interrupt request flag, lvf, is set, which occurs when the low voltage detector function detects a low power supply voltage. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low voltage interrupt enable bit, lve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the multi-function interrupt vector, will take place. when the low voltage interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the lvf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the compact and standard type tms have two interrupts each. all of the tm interrupts are contained within the multi-function interrupts. for each of the compact and standard type tms there are two interrupt request fags tnpf and tnaf and two enable bits tnpe and tnae. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. interrupt wake-up function each of the interrupt functions has the capability of waking up the microcontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function.
rev. 1.00 198 ???i? 0?? ?01? rev. 1.00 199 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request fags, mf0f~mf4f, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in the sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.00 198 ???i? 0?? ?01? rev. 1.00 199 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi low voltage detector C lvd each device has a low voltage detector function, also known as lvd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vlvd0, are used to select one of eight fxed voltages below which a low voltage condition will be determined. a low voltage condition is indicated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r r r/w r r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 unimplemented bit 5 lvdo: lvd output flag 0: no low voltage detect 1: low voltage detect bit 4 lvden: low voltage detector control 0: disable 1: enable bit 3 unimplemented bit 2~0 vlvd2~vlvd0: select lvd voltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.00 ?00 ???i? 0?? ?01? rev. 1.00 ?01 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi lvd operation the low voltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed voltage level stored in the lvdc register. this has a range of between 2.0v and 4.0v. when the power supply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power supply voltage condition. the low voltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. the low voltage detector also has its own interrupt which is contained within one of the multi-function interrupts, providing an alternative means of low voltage detection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the lvdo bit has been set high by a low voltage condition. when the device is powered down the low voltage detector will remain active if the lvden bit is high. in this case, the lvf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode. usb interface the usb interface is a 4-wire serial bus that allows communication between a host device and up to 127 max peripheral devices on the same bus. a token based protocol method is used by the host device for communication control. other advantages of the usb bus include live plugging and unplugging and dynamic device confguration. as the complexity of usb data protocol does not permit comprehensive usb operation information to be provided in this datasheet, the reader should therefore consult other external information for a detailed usb understanding. the devices include a usb interface function allowing for the convenient design of usb peripheral products. the usb disable/enable control bit usbdis is in the sysc register. if the usb is disabled, then v33o will be foating, the udp/udn lines will become i/o functions, and the usb sie will be disabled. power plane there are three power planes for HT66FB540/ht66fb550/ht66fb560: usb sie vdd, vddio and the mcu vdd. for the usb sie vdd will supply all circuits related to usb sie and be sourced from pin ubus. once the usb is removed from the usb and there is no power in the usb bus, the usb sie circuit is no longer operational. for the pa port, it can be configured using the paps1 and paps0 registers to define the pins pa0~pa7 are supplied by either the mcu vdd, the v33o or the power pin vddio. the pe0 is pin-shared with vddio and vref pins .the vddio function can be selected by configuration option and the vref function can be selected by the vrefs bit in the adcr1 register. however, the adref has the highest priority. if the vref function has been selected, the pe0 pin function will be disabled as well the vddio function, even though the vddio is selected.
rev. 1.00 ?00 ???i? 0?? ?01? rev. 1.00 ?01 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi for the mcu vdd, it supplies all the HT66FB540/ht66fb550/ht66fb560 circuits except the usb sie which is supply by ubus. the pe1 is pin shared with ubus pin and its input only. usb suspend wake-up remote wake-up if there is no signal on the usb bus for over 3ms, the devices will go into a suspend mode. the suspend flag, susp, in the usc register, will then be set high and an usb interrupt will be generated to indicate that the devices should jump to the suspend state to meet the requirements of the usb suspend current spec. in order to meet the requirements of the suspend current, the frmware should disable the usb clock by clearing the usbcken bit to 0. the suspend current can be further decreased by setting the susp2 bit in the ucc register. when the resume signal is sent out by the host, the devices will be woken up the by the usb interrupt and the resume bit in the usc register will be set. to ensure correct device operation, the program must set the usbcken bit in the ucc register high and clear the susp2 bit in the ucc register. the resume signal will be cleared before the idle signal is sent out by the host and the suspend line in the usc register will change to zero. so when the mcu detects the suspend bit in the usc register, the condition of the resume line should be noted and taken into consideration. the devices have a remote wake up function which can wake-up the usb host by sending a wake-up pulse through rmwk in the usc register. once the usb host receives a wake-up signal from the device it will send a resume signal to the devices.

rev. 1.00 ?0? ???i? 0?? ?01? rev. 1.00 ?0? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi usb interface operation the HT66FB540, ht66fb550 and ht66fb560 have 4 endpoints (ep0~ep3), 6 endpoints (ep0~ep5), and 8 endpoints (ep0~ep7) respectively. the ep0 supports control transfer. all ep1~ep7 support interrupt or bulk transfer. all endpoints except ep0 can be configure as 8, 16, 32, 64 fifo size by the register ufc0 and ufc1. ep0 has 8-byte fifo size. the total fifo size is 384+8 bytes for the HT66FB540, 640+8 bytes for the ht66fb550 and 896+8 bytes for the ht66fb560. as the usb fifo is assigned from the last bank of the data ram and has a start address of 0ffh to the upper address, dependent on the fifo size, if the corresponding data ram bank is used for both general purpose ram and the usb fifo, special care should be taken that the ram equ defnition should not overlap with the usb fifo ram address. the urd in the usc register is the usb reset signal control function defnition bit. the usb fifo size definition for in/out control depends on the ufc, ufien and ufoen registers. if out 1 not used, then the out 1 fifo will not be defned and in 2 will be defned as in 1 afterwards. n 80 h nbfh "n" = bank ? ~ 0 ? ?ast bank fi?st defined gene?a? pu??ose data memo?y out ? ( 8 bytes ) in ? ( 8 bytes ) out ? ( 16 bytes ) in ? ( 16 bytes ) out 1 ( 8 bytes ) in 1 ( 8 bytes ) nc 0 h nc 7 h nc 8 h ncfh nd 0 h ndfh ne 0 h nefh nf 0 h nf 7 h nf 8 h nffh ht 66 fb 540 usb fifo size defne
rev. 1.00 ?0? ???i? 0?? ?01? rev. 1.00 ?0? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi usb interface registers the usb interface has a series of registers associated with its operation. sysc register bit 7 6 5 4 3 2 1 0 name clk_?dj usbdis rubus hfv r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 clk_adj: pll clock automatic adjustment function pll related control bit, described elsewhere bit 6 usbdis: usb sie control bit 0: enable 1: disable bit 5 rubus: ubus pin pull low resistor 0: enable 1: disable bit 4~3 "": unimpleme nted, read as "0" bit 2 hfv : non-usb mode high frequency voltage control 0: for usb mode - bit must be cleared to zero. 1: for non-usb mode - bit must be set high. ensures that the higher frequency can work at lower voltages. a higher frequency is >8mhz and is used for the system clock f h . bit 1~0 "": unimpleme nted, read as "0" usb_stat register bit 7 6 5 4 3 2 1 0 name ps?_cko ps?_d?o ps?_cki ps?_d?i se1 se0 pu esd r/w w w r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ps2_cko: output for driving udp/gpio pin, when work under 3d ps2 mouse function. default value is 1. bit 6 ps2_dao: output for driving udn/gpio pin, when work under 3d ps2 mouse function. default value is 1. bit 5 ps2_cki: udp/gpio input bit 4 ps2_dai: udn/gpio input bit 3 se1 : this bit is used to indicate the sie has detected a se1 noise in the usb bus. this bit is set by sie and clear by f/w. bit 2 se0 : this bit is used to indicate the sie has detected a se0 noise in the usb bus. this bit is set by sie and clear by f/w. bit 1 pu: bit1=1, udp and udn have a 600k pull-high bit1=0, no pull-high (default on mcu reset) bit 0 this bit will set to 1 when there is esd issue. this bit is set by sie and cleared by f/w.
rev. 1.00 ?04 ???i? 0?? ?01? rev. 1.00 ?05 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi uint register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name ep?en ep?en ep1en ep0en r/w r r r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 unimplemented bit 3 ep3en: usb endpoint3 interrupt control bit. 0: disable 1: enable bit 2 ep2en: usb endpoint2 interrupt control bit. 0: disable 1: enable bit 1 ep1en: usb endpoint1 interrupt control bit. 0: disable 1: enable bit 0 ep0en: usb endpoint0 interrupt control bit. 0: disable 1: enable ? ht66fb550 bit 7 6 5 4 3 2 1 0 name ep5en ep4en ep?en ep?en ep1en ep0en r/w r r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 unimplemented bit 5 ep5en: usb endpoint5 interrupt control bit 0: disable 1: enable bit 4 ep4en: usb endpoint4 interrupt control bit 0: disable 1: enable bit 3 ep3en: usb endpoint3 interrupt control bit 0: disable 1: enable bit 2 ep2en: usb endpoint2 interrupt control bit 0: disable 1: enable bit 1 ep1en: usb endpoint1 interrupt control bit 0: disable 1: enable bit 0 ep0en: usb endpoint0 interrupt control bit 0: disable 1: enable
rev. 1.00 ?04 ???i? 0?? ?01? rev. 1.00 ?05 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb560 bit 7 6 5 4 3 2 1 0 name ep7en ep6en ep5en ep4en ep?en ep?en ep1en ep0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ep7en: usb endpoint7 interrupt control bit 0: disable 1: enable bit 6 ep6en: usb endpoint6 interrupt control bit 0: disable 1: enable bit 5 ep5en: usb endpoint5 interrupt control bit 0: disable 1: enable bit 4 ep4en: usb endpoint4 interrupt control bit 0: disable 1: enable bit 3 ep3en: usb endpoint3 interrupt control bit 0: disable 1: enable bit 2 ep2en: usb endpoint2 interrupt control bit 0: disable 1: enable bit 1 ep1en: usb endpoint1 interrupt control bit 0: disable 1: enable bit 0 ep0en: usb endpoint0 interrupt control bit 0: disable 1: enable
rev. 1.00 ?06 ???i? 0?? ?01? rev. 1.00 ?07 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi usc register bit 7 6 5 4 3 2 1 0 name urd selps? pll selusb resume urst rmwk susp r/w r/w r/w r/w r/w r r/w r/w r por 1 0 0 0 0 0 0 0 bit 7 urd: usb reset signal control function defnition 0: usb reset signal cannot mcu 1: usb reset signal will reset mcu bit 6 selps2: ps2 mode select bit 0: not ps2 mode 1: ps2 mode when the selps2 bit is set high, the ps2 function is selected and the pin-shared pins, udn/gpio0 and udp/gpio1, will become the gpio0 and gpio1 general purpose i/o functions which can be used to be the data and clk pins for the ps2. bit 5 pll: pll control bit 0: turn-on pll 1: turn-off pll bit 4 selusb: usb mode and v33o on/off select bit 0: not usb mode, turn-off v33o 1: usb mode, turn-on v33o when the selusb bit is set high, the usb and v33o functions are selected and the pin-share pins, udn/gpio0 and udp/gpio1, will become the udn and udp pins for the usb. bit 3 resume: usb resume indication bit 0: susp bit goes to 0 1: leave the suspend mode when the usb leaves the suspend mode, this bit is set to 1 (set by sie). when the resume is set by sie, an interrupt will be generated to wake-up the mcu. in order to detect the suspend state, the mcu should set usbcken and clear susp2 (in the ucc register) to enable the sie detect function. resume will be cleared when the susp goes to 0. when the mcu is detecting the susp, the condition of resume (causes the mcu to wake-up) should be noted and taken into consideration. bit 2 urst: usb reset indication bit 0: no usb reset 1: usb reset occurred this bit is set/cleared by the usb sie. this bit is used to detect a usb reset event on the usb bus. when this bit is set to 1, this indicates that a usb reset has occurred and that a usb interrupt will be initialized. bit 1 rmwk: usb remote wake-up command 0: no remote wake-up 1: remote wake-up it is set by mcu to leave the usb host leaving the suspend mode. indicate that the this bit is set to produce a high pulse width of 4 m s to indicate that the usb host has left the suspend mode. bit 0 susp: usb suspend indication 0: not in the suspend mode 1: enter the suspend mode when this bit is set to 1 (set by sie), it indicates that the usb bus has entered the suspend mode. the usb interrupt is also triggered when this bit changes from low to high.
rev. 1.00 ?06 ???i? 0?? ?01? rev. 1.00 ?07 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi selusb selps2 usb and ps2 mode description 0 0 1. no mode su??o?ted 2. v33o pin not output and it will foating ?. udn/gpio0 and udp/gpio1 ?ins cannt out?ut 0 1 1. ps? mode ?. v??o ?in out?ut vdd ?. udn/gpio0 and udp/gpio1 ?ins wi?? become the gpio0 and gpio1 pins, which can output by frmware 1 x 1. usb mode ?. v??o out?ut ?.?v ?. udn/gpio0 and udp/gpio1 ?ins wi?? become the udn and udp ?ins x: dont ca?e usr register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name ep?f ep?f ep1f ep0f r/w r r r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 8qlpsohphqwhg %lw ep3f: qgsrlqwdffhvvhgghwhfwlrq 1rwdffhvvhg ffhvvhg lw ep2f: qgsrlqwdffhvvhgghwhfwlrq 1rwdffhvvhg ffhvvhg lw ep1f: qgsrlqwdffhvvhgghwhfwlrq 1rwdffhvvhg ffhvvhg lw ep0f: qgsrlqwdffhvvhgghwhfwlrq 1rwdffhvvhg ffhvvhg
rev. 1.00 ?08 ???i? 0?? ?01? rev. 1.00 ?09 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb550 bit 7 6 5 4 3 2 1 0 name ep5f ep4f ep?f ep?f ep1f ep0f r/w r r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 unimplemented bit 5 ep5f: endpoint 5 accessed detection 0: not accessed 1: accessed bit 4 ep4f: endpoint 4 accessed detection 0: not accessed 1: accessed bit 3 ep3f: endpoint 3 accessed detection 0: not accessed 1: accessed bit 2 ep2f: endpoint 2 accessed detection 0: not accessed 1: accessed bit 1 ep1f: endpoint 1 accessed detection 0: not accessed 1: accessed bit 0 ep0f: endpoint 0 accessed detection 0: not accessed 1: accessed
rev. 1.00 ?08 ???i? 0?? ?01? rev. 1.00 ?09 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb560 bit 7 6 5 4 3 2 1 0 name ep7f ep6f ep5f ep4f ep?f ep?f ep1f ep0f r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ep7f: endpoint 7 accessed detection 0: not accessed 1: accessed bit 6 ep6f: endpoint 6 accessed detection 0: not accessed 1: accessed bit 5 ep5f: endpoint 5 accessed detection 0: not accessed 1: accessed bit 4 ep4f: endpoint 4 accessed detection 0: not accessed 1: accessed bit 3 ep3f: endpoint 3 accessed detection 0: not accessed 1: accessed bit 2 ep2f: endpoint 2 accessed detection 0: not accessed 1: accessed bit 1 ep1f: endpoint 1 accessed detection 0: not accessed 1: accessed bit 0 ep0f: endpoint 0 accessed detection 0: not accessed 1: accessed
rev. 1.00 ?10 ???i? 0?? ?01? rev. 1.00 ? 11 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ucc register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name rct?? sysclk fsys16mhz susp? usbcken eps1 eps0 r/w r/w r/w r/w r/w r/w r r/w r/w por 0 0 0 0 0 0 0 0 bit 7 rctrl: 7.5k resistor between udp and ubus control bit 0: no 7.5k resistor between udp and ubus 1: has 7.5k resistor between udp and ubus bit 6 sysclk: specify mcu oscillator frequency indication bit 0: 12mhz crystal oscillator or resonator, clear this bit to 0 1: 6mhz crystal oscillator or resonator, set this bit to 1 bit 5 fsys16mhz: mcu system clock source control bit 0: from osc 1: from pll output 16mhz bit 4 susp2: reduce power consumption in suspend mode control bit 0: in normal mode 1: in halt mode, set this bit to 1 for reducing power consumption bit 3 usbcken: usb clock control bit 0: disable 1: enable bit 2 unimplemented bit 1~0 eps1, eps0: accessing endpoint fifo selection 00: select endpoint 0 fifo (control) 01: select endpoint 1 fifo 10: select endpoint 2 fifo 11: select endpoint 3 fifo
rev. 1.00 ?10 ???i? 0?? ?01? rev. 1.00 ? 11 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb550 bit 7 6 5 4 3 2 1 0 name rct?? sysclk fsys16mhz susp? usbcken eps? eps1 eps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 rctrl: 7.5k resistor between udp and ubus control bit 0: no 7.5k resistor between udp and ubus 1: has 7.5k resistor between udp and ubus bit 6 sysclk: specify mcu oscillator frequency indication bit 0: 12mhz crystal oscillator or resonator, clear this bit to 0 1: 6mhz crystal oscillator or resonator, set this bit to 1 bit 5 fsys16mhz: mcu system clock source control bit 0: from osc 1: from pll output 16mhz bit 4 susp2: reduce power consumption in suspend mode control bit 0: in normal mode 1: in halt mode, set this bit to 1 for reducing power consumption bit 3 usbcken: usb clock control bit 0: disable 1: enable bit 2~0 eps2, eps1, eps0: accessing endpoint fifo selection 000: select endpoint 0 fifo (control) 001: select endpoint 1 fifo 010: select endpoint 2 fifo 011: select endpoint 3 fifo 100: select endpoint 4 fifo 101~111: select endpoint 5 fifo
rev. 1.00 ?1? ???i? 0?? ?01? rev. 1.00 ?1? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb560 bit 7 6 5 4 3 2 1 0 name rct?? sysclk fsys16mhz susp? usbcken eps? eps1 eps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 rctrl: 7.5k resistor between udp and ubus control bit 0: no 7.5k resistor between udp and ubus 1: has 7.5k resistor between udp and ubus bit 6 sysclk: specify mcu oscillator frequency indication bit 0: 12mhz crystal oscillator or resonator, clear this bit to 0 1: 6mhz crystal oscillator or resonator, set this bit to 1 bit 5 fsys16mhz: mcu system clock source control bit 0: from osc 1: from pll output 16mhz bit 4 susp2: reduce power consumption in suspend mode control bit 0: in normal mode 1: in halt mode, set this bit to 1 for reducing power consumption bit 3 usbcken: usb clock control bit 0: disable 1: enable bit 2~0 eps2, eps1, eps0: accessing endpoint fifo selection 000: select endpoint 0 fifo (control) 001: select endpoint 1 fifo 010: select endpoint 2 fifo 011: select endpoint 3 fifo 100: select endpoint 4 fifo 101: select endpoint 5 fifo 110: select endpoint 6 fifo 111: select endpoint 7 fifo
rev. 1.00 ?1? ???i? 0?? ?01? rev. 1.00 ?1? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi awr register bit 7 6 5 4 3 2 1 0 name ?d6 ?d5 ?d4 ?d? ?d? ?d1 ?d0 wken r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~1 ad6~ad0: usb device address bit 0 wken: usb remote-wake-up control bit 0: disable 1: enable the awr register contains the current address and a remote wake up function control bit. the initial value of awr is 00h. the address value extracted from the usb command has not to be loaded into this register until the setup stage has fnished. stlo register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name stlo? stlo? stlo1 stlo0 r/w r r r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 unimplemented bit 3~0 stlo3~stlo0: fifo out stall endpoints indication bits 0: not stall 1: stall the stall register shows if the corresponding endpoint has worked properly or not. as soon as endpoint improper operation occurs, the related bit in the stall register has to be set high. the stall register bits will be cleared by a usb reset signal and a setup token event. ? ht66fb550 bit 7 6 5 4 3 2 1 0 name stlo5 stlo4 stlo? stlo? stlo1 stlo0 r/w r r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 unimplemented bit 5~0 stlo5~stlo0: fifo out stall endpoints indication bits 0: not stall 1: stall the stall register shows if the corresponding endpoint has worked properly or not. as soon as endpoint improper operation occurs, the related bit in the stall register has to be set high. the stall register bits will be cleared by a usb reset signal and a setup token event.
rev. 1.00 ?14 ???i? 0?? ?01? rev. 1.00 ?15 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb560 bit 7 6 5 4 3 2 1 0 name stlo7 stlo6 stlo5 stlo4 stlo? stlo? stlo1 stlo0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 stlo7~stlo0: fifo out stall endpoints indication bits 0: not stall 1: stall the stall register shows if the corresponding endpoint has worked properly or not. as soon as endpoint improper operation occurs, the related bit in the stall register has to be set high. the stall register bits will be cleared by a usb reset signal and a setup token event. stli register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name stli? stli? stli1 stli0 r/w r r r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 unimplemented bit 3~0 stli3~stli0: fifo in stall endpoints indication bits 0: not stall 1: stall the stall register shows if the corresponding endpoint has worked properly or not. as soon as endpoint improper operation occurs, the related bit in the stall register has to be set high. the stall register bits will be cleared by a usb reset signal and a setup token event. ? ht66fb550 bit 7 6 5 4 3 2 1 0 name stli5 stli4 stli? stli? stli1 stli0 r/w r r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 unimplemented bit 5~0 stli5~stli0: fifo in stall endpoints indication bits 0: not stall 1: stall the stall register shows if the corresponding endpoint has worked properly or not. as soon as endpoint improper operation occurs, the related bit in the stall register has to be set high. the stall register bits will be cleared by a usb reset signal and a setup token event.
rev. 1.00 ?14 ???i? 0?? ?01? rev. 1.00 ?15 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb560 bit 7 6 5 4 3 2 1 0 name stli7 stli6 stli5 stli4 stli? stli? stli1 stli0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 stli7~stli0: fifo in stall endpoints indication bits 0: not stall 1: stall the stall register shows if the corresponding endpoint has worked properly or not. as soon as endpoint improper operation occurs, the related bit in the stall register has to be set high. the stall register bits will be cleared by a usb reset signal and a setup token event. sies register bit 7 6 5 4 3 2 1 0 name nmi crcf n?k in out err ?set r/w r/w r/w r r r r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 nmi: nak token interrupt mask fag 0: interrupt enable 1: interrupt disable if this bit set, when the device sent a nak token to the host, an interrupt will be disabled. otherwise if this bit is cleared, when the device sends a nak token to the host, it will enter the interrupt sub-routine. this bit is used for all endpoint. bit 6 crcf: crc error detection fag 0: no error 1: error this bit will be set to 1 when there are the following three conditions happened: crc error, pid error, bit stuffng error. this bit is set by sie and cleared by f/w. bit 5 unimplemented bit 4 nak: ack error detection fag 0: no error 1: error this bit will set to 1 once sie discover there are some error condition so the sie is not response (nak or ack or data) for the usb token. this bit is set by sie and cleared by f/w. bit 3 in: current usb receiving signal indicator 0: low 1: high this bit is used to indicate the current usb receiving signal from pc host is in token. bit 2 out: usb out token indicator 0: low 1: high this bit is used to indicate the out token (except the out zero length token) has been received. the frmware clears this bit after the out data has been read. also, this bit will be cleared by sie after the next valid setup token is received. bit 1 err: fifo accessed error indicator 0: no error 1: error this bit is used to indicate that some errors have occurred when the fifo is accessed. this bit is set by sie and should be cleared by firmware. this bit is used for all endpoint.
rev. 1.00 ?16 ???i? 0?? ?01? rev. 1.00 ?17 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi bit 0 aset: device address updated method control bit 0: update address after an written address to the awr register 1: update address after pc host read out data this bit is used to confgure the sie to automatically change the device address by the value stored in the awr register. when this bit is set to 1 by frmware, the sie will update the device address by the value stored in the awr register after the pc host has successfully read the data from he device by an in operation. otherwise, when this bit is cleared to 0, the sie will update the device address immediately after an address is written to the awr register. so, in order to work properly, the frmware has to clear this bit after a next valid setup token is received. misc register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name len0 re?dy setcmd e?idf cle?r tx request r/w r r r/w r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 len0: 0-sized packet indication fag 0: not 0-sized packet 1: 0-sized packet this bit is used to show that the host sent a 0-sized packet to the mcu. this bit must be cleared by a read action to the corresponding fifo. bit 6 ready: desired fifo ready indication fag 0: not ready 1: ready bit 5 setcmd: setup command indication fag 0: not setup command 1: setup command this bit is used to show that the data in the fifo is a setup command. this bit is set by hardware and cleared by firmware. bit 4 unimplemented bit 3 e3idf: endpoint 3 input fifo selection 0: single buffer 1: double buffer bit 2 clear: clear fifo function control bit 0: disable 1: enable mcu requests to clear the fifo, even if the fifo is not ready. after clearing the fifo, the usb interface will send force_tx_err to tell the host that data under-run if the host wants to read data. bit 1 tx: data writing to fifo status indication fag 0: data writing fnished 1: data writing to fifo to represent the direction and transition end mcu access. when set to logic 1, the mcu desires to write data to the fifo. after fnishing, this bit must be set to logic 0 before terminating request to represent transition end. for an mcu read operation, this bit must be set to logic 0 and set to logic 1 after fnishing. bit 0 request: desired fifo request status indication fag 0: no request 1: request after setting the status of the desired one, fifo can be requested by setting this bit high. after fnishing, this bit must be set low.
rev. 1.00 ?16 ???i? 0?? ?01? rev. 1.00 ?17 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb550/ht66fb560 bit 7 6 5 4 3 2 1 0 name len0 re?dy setcmd e4odf e?idf cle?r tx request r/w r r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 len0: 0-sized packet indication fag 0: not 0-sized packet 1: 0-sized packet this bit is used to show that the host sent a 0-sized packet to the mcu. this bit must be cleared by a read action to the corresponding fifo. bit 6 ready: desired fifo ready indication fag 0: not ready 1: ready bit 5 setcmd: setup command indication fag 0: not setup command 1: setup command this bit is used to show that the data in the fifo is a setup command. this bit is set by hardware and cleared by firmware. bit 4 e4odf: endpoint 4 output fifo selection 0: single buffer 1: double buffer bit 3 e3idf: endpoint 3 input fifo selection 0: single buffer 1: double buffer bit 2 clear: clear fifo function control bit 0: disable 1: enable mcu requests to clear the fifo, even if the fifo is not ready. after clearing the fifo, the usb interface will send force_tx_err to tell the host that data under-run if the host wants to read data. bit 1 tx: data writing to fifo status indication fag 0: data writing fnished 1: data writing to fifo to represent the direction and transition end mcu access. when set to logic 1, the mcu desires to write data to the fifo. after fnishing, this bit must be set to logic 0 before terminating request to represent transition end. for an mcu read operation, this bit must be set to logic 0 and set to logic 1 after fnishing. bit 0 request: desired fifo request status indication fag 0: no request 1: request after setting the status of the desired one, fifo can be requested by setting this bit high. after fnishing, this bit must be set low.
rev. 1.00 ?18 ???i? 0?? ?01? rev. 1.00 ?19 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ufoen register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name seto ? seto ? seto1 d ?t? tg r/w r r r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 unimplemented bit 3 seto3: ep3 output fifo control bit 0: disable 1: enable bit 2 seto2: ep2 output fifo control bit 0: disable 1: enable bit 1 seto1: ep1 output fifo control bit 0: disable 1: enable bit 0 datatg: data token toggle bit 0: low 1: high ? ht66fb550 bit 7 6 5 4 3 2 1 0 name seto5 seto4 seto ? seto ? seto1 d ?t? tg r/w r r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 unimplemented bit 5 seto5: ep5 output fifo control bit 0: disable 1: enable bit 4 seto4: ep4 output fifo control bit 0: disable 1: enable bit 3 seto3: ep3 output fifo control bit 0: disable 1: enable bit 2 seto2: ep2 output fifo control bit 0: disable 1: enable bit 1 seto1: ep1 output fifo control bit 0: disable 1: enable bit 0 datatg: data token toggle bit 0: low 1: high
rev. 1.00 ?18 ???i? 0?? ?01? rev. 1.00 ?19 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb560 bit 7 6 5 4 3 2 1 0 name seto7 seto6 seto5 seto4 seto ? seto ? seto1 d ?t? tg r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 seto7: ep7 output fifo control bit 0: disable 1: enable bit 6 seto6: ep6 output fifo control bit 0: disable 1: enable bit 5 seto5: ep5 output fifo control bit 0: disable 1: enable bit 4 seto4: ep4 output fifo control bit 0: disable 1: enable bit 3 seto3: ep3 output fifo control bit 0: disable 1: enable bit 2 seto2: ep2 output fifo control bit 0: disable 1: enable bit 1 seto1: ep1 output fifo control bit 0: disable 1: enable bit 0 datatg: data token toggle bit 0: low 1: high
rev. 1.00 ??0 ???i? 0?? ?01? rev. 1.00 ??1 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ufien register ? HT66FB540 bit 7 6 5 4 3 2 1 0 name seti? seti? seti1 fifo_def r/w r r r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 unimplemented bit 3 seti3: ep3 input fifo control bit 0: disable 1: enable bit 2 seti2: ep2 input fifo control bit 0: disable 1: enable bit 1 seti1: ep1 input fifo control bit 0: disable 1: enable bit 0 fifo_def: fifo confguration redefned control bit 0: disable 1: enable if this bit is set to 1, the sie should redefne the fifo confguration. this bit will be automatically cleared by sie. ? ht66fb550 bit 7 6 5 4 3 2 1 0 name seti5 seti4 seti? seti? seti1 fifo_def r/w r r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 unimplemented bit 5 seti5: ep5 input fifo control bit 0: disable 1: enable bit 4 seti4: ep4 input fifo control bit 0: disable 1: enable bit 3 seti3: ep3 input fifo control bit 0: disable 1: enable bit 2 seti2: ep2 input fifo control bit 0: disable 1: enable bit 1 seti1: ep1 input fifo control bit 0: disable 1: enable bit 0 fifo_def: fifo confguration redefned control bit 0: disable 1: enable if this bit is set to 1, the sie should redefne the fifo confguration. this bit will be automatically cleared by sie.
rev. 1.00 ??0 ???i? 0?? ?01? rev. 1.00 ??1 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ? ht66fb560 bit 7 6 5 4 3 2 1 0 name seti7 seti6 seti5 seti4 seti? seti? seti1 fifo_def r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 seti7: ep7 input fifo control bit 0: disable 1: enable bit 6 seti6: ep6 input fifo control bit 0: disable 1: enable bit 5 seti5: ep5 input fifo control bit 0: disable 1: enable bit 4 seti4: ep4 input fifo control bit 0: disable 1: enable bit 3 seti3: ep3 input fifo control bit 0: disable 1: enable bit 2 seti2: ep2 input fifo control bit 0: disable 1: enable bit 1 seti1: ep1 input fifo control bit 0: disable 1: enable bit 0 fifo_def: fifo confguration redefned control bit 0: disable 1: enable if this bit is set to 1, the sie should redefne the fifo confguration. this bit will be automatically cleared by sie. ufc0 register bit 7 6 5 4 3 2 1 0 name e?fs1 e?fs0 e?fs1 e?fs0 e1fs1 e1fs0 r/w r/w r/w r/w r/w r/w r/w r r por 0 0 0 0 0 0 0 0 bit 7, 6 e3fs1, e3sf0: endpoint 3 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte bit 5, 4 e2fs1, e2sf0: endpoint 2 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte bit 3, 2 e1fs1, e1sf0: endpoint 1 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte bit 1~0 unimplemented
rev. 1.00 ??? ???i? 0?? ?01? rev. 1.00 ??? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ufc1 register ? ht66fb550 bit 7 6 5 4 3 2 1 0 name e5fs1 e5fs0 e4fs1 e4fs0 r/w r r r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 unimplemented bit 3, 2 e5fs1, e5sf0: endpoint 5 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte bit 1, 0 e4fs1, e4sf0: endpoint 4 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte ? ht66fb560 bit 7 6 5 4 3 2 1 0 name e7fs1 e7fs0 e6fs1 e6fs0 e5fs1 e5fs0 e4fs1 e4fs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7, 6 e7fs1, e7sf0: endpoint 7 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte bit 5, 4 e6fs1, e6sf0: endpoint 6 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte bit 3, 2 e5fs1, e5sf0: endpoint 5 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte bit 1, 0 e4fs1, e4sf0: endpoint 4 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte
rev. 1.00 ??? ???i? 0?? ?01? rev. 1.00 ??? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi usb endpoint accessing registers ? HT66FB540 register name bit 7 6 5 4 3 2 1 0 fifo0 d7 d6 d5 d4 d? d? d1 d0 fifo1 d7 d6 d5 d4 d? d? d1 d0 fifo? d7 d6 d5 d4 d? d? d1 d0 fifo? d7 d6 d5 d4 d? d? d1 d0 ? ht66fb550 register name bit 7 6 5 4 3 2 1 0 fifo0 d7 d6 d5 d4 d? d? d1 d0 fifo1 d7 d6 d5 d4 d? d? d1 d0 fifo? d7 d6 d5 d4 d? d? d1 d0 fifo? d7 d6 d5 d4 d? d? d1 d0 fifo4 d7 d6 d5 d4 d? d? d1 d0 fifo5 d7 d6 d5 d4 d? d? d1 d0 ? ht66fb560 register name bit 7 6 5 4 3 2 1 0 fifo0 d7 d6 d5 d4 d? d? d1 d0 fifo1 d7 d6 d5 d4 d? d? d1 d0 fifo? d7 d6 d5 d4 d? d? d1 d0 fifo? d7 d6 d5 d4 d? d? d1 d0 fifo4 d7 d6 d5 d4 d? d? d1 d0 fifo5 d7 d6 d5 d4 d? d? d1 d0 fifo6 d7 d6 d5 d4 d? d? d1 d0 fifo7 d7 d6 d5 d4 d? d? d1 d0
rev. 1.00 ??4 ???i? 0?? ?01? rev. 1.00 ??5 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi confguration options confguration options refer to certain options within the mcu that are programmed into the devices during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the devices using the hardware programming tools, once they are selected they cannot be changed later using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator options 1 high s?eed system osci??ato? se?ection C f h : 1. hirc (defau?t) ?. hxt ? low s?eed system osci??ato? se?ection C f l : 1. lirc (defau?t) ?. lxt ? f sub c?ock se?ection: 1. lirc (defau?t) ?. lxt 4 time base c ?ock se?ection C f tbc : 1. lirc (defau?t) ?. lxt crystal mode frequency option 5 c?ock mode f?equency: 1. 1?mhz ?. 6mhz i/o or vddio option 6 i/o o? vddio ?in cont?o? bit: 1. vddio (defau?t) ?. i/o (pe0)
rev. 1.00 ??4 ???i? 0?? ?01? rev. 1.00 ??5 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi application circuits vdd/ubus vss 100k res vdd v??o udn udp sim hvdd ?00 0.1f spi / i ? c device i/o tp0 tp1 tp? vdd b g r 1k 65 1?0 q1 ?904 q? ?904 q? ?904 vbus d- d+ vss 0.1f 0.1f 10f 47?f 47?f ?? key mat?ix in?ut ?n0~15 ?na?og in?ut 10?f 10?f ??768hz cn+ cn- cno ?na?og in?ut/ out?ut 10m xt1 xt? 0.1f 56 1k 1k ??
rev. 1.00 ??6 ???i? 0?? ?01? rev. 1.00 ??7 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontroller, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.00 ??6 ???i? 0?? ?01? rev. 1.00 ??7 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.00 ??8 ???i? 0?? ?01? rev. 1.00 ??9 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic ?dd ??[m] ?dd data memo?y to ?cc 1 z? c? ?c? ov ?ddm ??[m] ?dd ?cc to data memo?y 1 note z? c? ?c? ov ?dd ??x ?dd immediate data to ?cc 1 z? c? ?c? ov ?dc ??[m] ?dd data memo?y to ?cc with ca??y 1 z? c? ?c? ov ?dcm ??[m] ?dd ?cc to data memo?y with ca??y 1 note z? c? ?c? ov sub ??x subt?act immediate data f?om the ?cc 1 z? c? ?c? ov sub ??[m] subt?act data memo?y f?om ?cc 1 z? c? ?c? ov subm ??[m] subt?act data memo?y f?om ?cc with ?esu?t in data memo?y 1 note z? c? ?c? ov sbc ??[m] subt?act data memo?y f?om ?cc with ca??y 1 z? c? ?c? ov sbcm ??[m] subt?act data memo?y f?om ?cc with ca??y ? ?esu?t in data memo?y 1 note z? c? ?c? ov d?? [m] decima? adjust ?cc fo? ?ddition with ?esu?t in data memo?y 1 note c logic operation ?nd ??[m] logica? ?nd data memo?y to ?cc 1 z or ??[m] logica? or data memo?y to ?cc 1 z xor ??[m] logica? xor data memo?y to ?cc 1 z ?ndm ??[m] logica? ?nd ?cc to data memo?y 1 note z orm ??[m] logica? or ?cc to data memo?y 1 note z xorm ??[m] logica? xor ?cc to data memo?y 1 note z ?nd ??x logica? ?nd immediate data to ?cc 1 z or ??x logica? or immediate data to ?cc 1 z xor ??x logica? xor immediate data to ?cc 1 z cpl [m] com??ement data memo?y 1 note z cpl? [m] com??ement data memo?y with ?esu?t in ?cc 1 z increment & decrement inc? [m] inc?ement data memo?y with ?esu?t in ?cc 1 z inc [m] inc?ement data memo?y 1 note z dec? [m] dec?ement data memo?y with ?esu?t in ?cc 1 z dec [m] dec?ement data memo?y 1 note z rotate rr? [m] rotate data memo?y ?ight with ?esu?t in ?cc 1 none rr [m] rotate data memo?y ?ight 1 note none rrc? [m] rotate data memo?y ?ight th?ough ca??y with ?esu?t in ?cc 1 c rrc [m] rotate data memo?y ?ight th?ough ca??y 1 note c rl? [m] rotate data memo?y ?eft with ?esu?t in ?cc 1 none rl [m] rotate data memo?y ?eft 1 note none rlc? [m] rotate data memo?y ?eft th?ough ca??y with ?esu?t in ?cc 1 c rlc [m] rotate data memo?y ?eft th?ough ca??y 1 note c
rev. 1.00 ??8 ???i? 0?? ?01? rev. 1.00 ??9 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi mnemonic description cycles flag affected data move mov ??[m] move data memo?y to ?cc 1 none mov [m]?? move ?cc to data memo?y 1 note none mov ??x move immediate data to ?cc 1 none bit operation clr [m].i c?ea? bit of data memo?y 1 note none set [m].i set bit of data memo?y 1 note none branch jmp add ? jum? unconditiona??y ? none sz [m] ski? if data memo?y is ze?o 1 note none sz? [m] ski? if data memo?y is ze?o with data movement to ?cc 1 note none sz [m].i ski? if bit i of data memo?y is ze?o 1 note none snz [m].i ski? if bit i of data memo?y is not ze?o 1 note none siz [m] ski? if inc?ement data memo?y is ze?o 1 note none sdz [m] ski? if dec?ement data memo?y is ze?o 1 note none siz? [m] ski? if inc?ement data memo?y is ze?o with ?esu?t in ?cc 1 note none sdz? [m] ski? if dec?ement data memo?y is ze?o with ?esu?t in ?cc 1 note none c? ll add? sub?outine ca?? ? none ret retu?n f?om sub?outine ? none ret ??x retu?n f?om sub?outine and ?oad immediate data to ?cc ? none reti retu?n f?om inte??u?t ? none table read t ?brd [m] read tab? e to tblh and data memo?y ? note none t ? brdl [m] read tab?e (?ast ? age) to tblh and data memo?y ? note none miscellaneous nop no o?e?ation 1 none clr [m] c?ea? data memo?y 1 note none set [m] set data memo?y 1 note none clr wdt c?ea? watchdog time? 1 to ? pdf clr wdt1 p?e-c?ea? watchdog time? 1 to ? pdf clr wdt? p?e-c?ea? watchdog time? 1 to ? pdf sw ? p [m] swa? nibb?es of data memo?y 1 note none sw ?p ? [m] swa? nibb?es of data memo?y with ?esu?t in ?cc 1 none h? lt ente? ?owe? down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf fags remain unchanged.
rev. 1.00 ??0 ???i? 0?? ?01? rev. 1.00 ??1 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi instruction defnition ?dd data memo?y to ?cc with ca??y the contents of the specifed data memory, accumulator and the carry fag are added. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc + [m] + c ov ? z? ?c? c ?dd ?cc to data memo?y with ca??y the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. [m] ?cc + [m] + c ov ? z? ?c? c ?dd data memo?y to ?cc the contents of the specifed data memory and the accumulator are added. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc + [m] ov ? z? ?c? c ?dd immediate data to ?cc the contents of the accumulator and the specifed immediate data are added. the ?esu?t is sto?ed in the ?ccumu?ato? . ?c ?cc + x ov ? z? ?c? c ?dd ?cc to data memo?y the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. [m] ?cc + [m] ov ? z? ?c? c logica? ?nd data memo?y to ?cc data in the accumulator and the specifed data memory perform a bitwise logical ?nd o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc ?nd [m] z logica? ?nd immediate data to ?cc data in the ?ccumu?ato? and the s?ecified immediate data ?e?fo? m a bitwise ?ogica? ?nd o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc ?nd x z logica? ?nd ?cc to data memo?y data in the specifed data memory and the accumulator perform a bitwise logical ?nd o?e? ation. the ?esu?t is sto?ed in the data memo? y. [m] ?cc ?nd [m] z adc a,[m] desc?i?tion o?e?ation affected fag(s) adcm a,[m] desc?i?tion o?e?ation affected fag(s) add a,[m] desc?i?tion o?e?ation affected fag(s) add a,x desc?i?tion o?e?ation affected fag(s) addm a,[m] desc?i?tion o?e?ation affected fag(s) and a,[m] desc?i?tion o?e?ation affected fag(s) and a,x desc?i?tion o?e?ation affected fag(s) andm a,[m] desc?i?tion o?e?ation affected fag(s)
rev. 1.00 ??0 ???i? 0?? ?01? rev. 1.00 ??1 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi sub?outine ca?? unconditionally calls a subroutine at the specifed address. the program counter then inc ? ements by 1 to obtain the add? ess of the next inst ? uction which is then ? ushed onto the stack. the s?ecified add?ess is then ?oaded and the ??og? am continues execution f ? om this new add ? ess. ? s this inst? uction ? equi ? es an additiona? o?e?ation? it is a two cyc?e inst?uction. stack p?og?am counte? + 1 p?og?am counte? add? none c?ea? data memo?y each bit of the specifed data memory is cleared to 0. [m] 00h none c?ea? bit of data memo?y bit i of the specifed data memory is cleared to 0. [m].i 0 none c?ea? watchdog time? the to, pdf fags and the wdt are all cleared. wdt c ?ea?ed to 0 pdf 0 to ? pdf p?e-c?ea? watchdog time? the to, pdf fags and the wdtare all cleared. note that this instruction works in conjunction with clr wdt ? and must be executed a?te?nate? y with clr wdt? to have effect. re ?etitive? y executing this inst? uction without a?te?nate? y executing clr wdt? wi?? have no effect. wdt c ?ea?ed to 0 pdf 0 to ? pdf p?e-c?ea? watchdog time? the to, pdf fags and the wdtare all cleared. note that this instruction works in conjunction with clr wdt1 and must be executed a ?te?nate? y with clr wdt1 to have effect. re ?etitive? y executing this inst? uction without a?te?nate? y executing wdt c ?ea?ed to 0 pdf 0 to ? pdf call addr desc?i?tion o?e?ation affected fag(s) clr [m] desc?i?tion o?e?ation affected fag(s) clr [m].i desc?i?tion o?e?ation affected fag(s) clr wdt desc?i?tion o?e?ation affected fag(s) clr wdt1 desc?i?tion o?e?ation affected fag(s) clr wdt2 desc?i?tion o?e?ation affected fag(s)
rev. 1.00 ??? ???i? 0?? ?01? rev. 1.00 ??? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi com??ement data memo?y each bit of the s ?ecified data memo? y is ?ogica??y com?? emented (1 ' s com ?? ement). bits which ?? evious ? y contained a 1 a? e changed to 0 and vice ve?sa. [m] [m] z com??ement data memo?y with ?esu?t in ?cc each bit of the s ?ecified data memo? y is ?ogica??y com?? emented (1 ' s com ?? ement). bits which ?? evious ? y contained a 1 a? e changed to 0 and vice ve? sa. the com??emented ?esu?t is sto?ed in the ?ccumu?ato? and the contents of the data memo?y ?emain unchanged. ?cc [m] z decima?-?djust ?cc fo? addition with ?esu?t in data memo?y conve?t the contents of the ?ccumu?ato? va?ue to a bcd ( bina? y coded decima?) va?ue ?esu? ting f?om the ?? evious addition of two bcd va?iab? es. if the ?ow nibb?e is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibb? e. othe? wise the ? ow nibb?e ? emains unchanged. if the high nibb? e is g?eate? than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentia??y ? the decima? conve?sion is ?e?fo?med by adding 00h? 06h? 60h o? 66h depending on the accumulator and fag conditions. only the c fag may be affected by this inst ? uction which indicates that if the o?igina? bcd sum is g?eate? than 100? it a??ows mu?ti??e ??ecision decima? addition. [m] ?cc + 00h o? [m] ?cc + 06h o? [m] ?cc + 60h o? [m] ?cc + 66h c dec?ement data memo?y data in the specifed data memory is decremented by 1. [m] [m] D 1 z dec?ement data memo?y with ?esu?t in ?cc data in the specifed data memory is decremented by 1. the result is stored in the ?ccumu?ato? . the contents of the data memo ?y ?emain unchanged. ?cc [m] D 1 z cpl [m] desc?i?tion o?e?ation affected fag(s) cpla [m] desc?i?tion o?e?ation affected fag(s) daa [m] desc?i?tion o?e?ation affected fag(s) dec [m] desc?i?tion o?e?ation affected fag(s) deca [m] desc?i?tion o?e?ation affected fag(s)
rev. 1.00 ??? ???i? 0?? ?01? rev. 1.00 ??? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ente? ?owe? down mode this inst?uction sto?s the ??og?am execution and tu? ns off the system c? ock. the contents of the data memo ?y and ?egiste?s a?e ? etained. the wdt and ??esca?e? a? e c?ea? ed. the ?owe? down f? ag pdf is set and the wdt time-out f? ag to is c?ea?ed. to 0 pdf 0 to ? pdf inc?ement data memo?y data in the specifed data memory is incremented by 1. [m] [m]+1 z inc?ement data memo?y with ?esu?t in ?cc data in the specifed data memory is incremented by 1. the result is stored in the ?ccumu?ato? . the contents of the data memo ?y ?emain unchanged. ?cc [m]+1 z jum? unconditiona??y the contents of the p ?og? am counte? a?e ?e?? aced with the s? ecified add? ess. p? og ? am execution then continues f? om this new add ? ess. ? s this ? equi ? es the inse? tion of a dummy inst?uction whi?e the new add?ess is ?oaded? it is a two cyc?e inst?uction. p?og?am counte? add? none move data memo?y to ?cc the contents of the specifed data memory are copied to the accumulator. ?cc [m] none move immediate data to ?cc the immediate data specifed is loaded into the accumulator. ?cc x none move ?cc to data memo?y the contents of the accumulator are copied to the specifed data memory. [m] ?cc none no o?e?ation no o?e?ation is ?e?fo?med. execution continues with the next inst?uction. no o?e?ation none halt desc?i?tion o?e?ation affected fag(s) inc [m] desc?i?tion o?e?ation affected fag(s) inca [m] desc?i?tion o?e?ation affected fag(s) jmp addr desc?i?tion o?e?ation affected fag(s) mov a,[m] desc?i?tion o?e?ation affected fag(s) mov a,x desc?i?tion o?e?ation affected fag(s) mov [m],a desc?i?tion o?e?ation affected fag(s) nop desc?i?tion o?e?ation affected fag(s)
rev. 1.00 ??4 ???i? 0?? ?01? rev. 1.00 ??5 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi logica? or data memo?y to ?cc data in the accumulator and the specifed data memory perform a bitwise logical or o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " or " [m] z logica? or immediate data to ?cc data in the ?ccumu?ato? and the s?ecified immediate data ?e?fo? m a bitwise ?ogica? or o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " or " x z logica? or ?cc to data memo?y data in the specifed data memory and the accumulator perform a bitwise logical or o?e? ation. the ?esu?t is sto?ed in the data memo? y. [m] ?cc " or " [m] z retu?n f?om sub?outine the p?og?am counte? is ?esto?ed f? om the stack. p?og?am execution continues at the ?esto?ed add?ess. p?og?am counte? stack none retu?n f?om sub?outine and ?oad immediate data to ?cc the p?og?am counte? is ?esto?ed f?om the stack and the ?ccumu?ato? ? oaded with the specifed immediate data. program execution continues at the restored add?ess. p?og?am counte? stack ?cc x none retu?n f?om inte??u?t the p?og?am counte? is ?esto?ed f? om the stack and the inte??u?ts a?e ?e-enab?ed by setting the emi bit. emi is the maste ? inte??u?t g?oba? enab? e bit. if an inte??u?t was ? ending when the reti inst? uction is executed? the ? ending inte??u?t ?outine wi?? be ??ocessed befo?e ?etu?ning to the main ??og?am. p?og?am counte? stack emi 1 none rotate data memo?y ?eft the contents of the s ? ecified data memo ?y a ? e ? otated ? eft by 1 bit with bit 7 ?otated into bit 0. [m].(i+1) [m].i; (i=0~6) [m].0 [m].7 none or a,[m] desc?i?tion o?e?ation affected fag(s) or a,x desc?i?tion o?e?ation affected fag(s) orm a,[m] desc?i?tion o?e?ation affected fag(s) ret desc?i?tion o?e?ation affected fag(s) ret a,x desc?i?tion o?e?ation affected fag(s) reti desc?i?tion o?e?ation affected fag(s) rl [m] desc?i?tion o?e?ation affected fag(s)
rev. 1.00 ??4 ???i? 0?? ?01? rev. 1.00 ??5 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi . rotate data memo?y ?eft with ?esu?t in ?cc the contents of the s?ecified data memo?y a?e ?otated ? eft by 1 bit with bit 7 ? otated into bit 0. the ?otated ?esu?t is sto?ed in the ?ccumu?ato? and the contents of the data memo?y ?emain unchanged. ?cc.(i+1) [m].i; (i=0~6) ?cc.0 [m].7 none rotate data memo?y ?eft th?ough ca??y the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. [m].(i+1) [m].i; (i=0~6) [m].0 c c [m].7 c rotate data memo?y ?eft th?ough ca??y with ?esu?t in ?cc data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the ?otated ?esu?t is sto? ed in the ?ccumu?ato? and the contents of the data memo?y ?emain unchanged. ?cc.(i+1) [m].i; (i=0~6) ?cc.0 c c [m].7 c rotate data memo?y ?ight the contents of the specifed data memory are rotated right by 1 bit with bit 0 ?otated into bit 7. [m].i [m].(i+1); (i=0~6) [m].7 [m].0 none rotate data memo?y ?ight with ?esu?t in ?cc data in the specifed data memory and the carry fag are rotated right by 1 bit with bit 0 ? otated into bit 7. the ?otated ?esu?t is sto?ed in the ?ccumu?ato ? and the contents of the data memo?y ?emain unchanged. ?cc.i [m].(i+1); (i=0~6) ?cc.7 [m].0 none rotate data memo?y ?ight th?ough ca??y the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. [m].i [m].(i+1); (i=0~6) [m].7 c c [m].0 c rla [m] desc?i?tion o?e?ation affected fag(s) rlc [m] desc?i?tion o?e?ation affected fag(s) rlca [m] desc?i?tion o?e?ation affected fag(s) rr [m] desc?i?tion o?e?ation affected fag(s) rra [m] desc?i?tion o?e?ation affected fag(s) rrc [m] desc?i?tion o?e?ation affected fag(s)
rev. 1.00 ??6 ???i? 0?? ?01? rev. 1.00 ??7 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi rotate data memo?y ?ight th?ough ca??y with ?esu?t in ?cc data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated ?esu?t is sto?ed in the ?ccumu?ato? and the contents of the data memo?y ? emain unchanged. ?cc.i [m].(i+1); (i=0~6) ?cc.7 c c [m].0 c subt?act data memo?y f?om ?cc with ca??y the contents of the specifed data memory and the complement of the carry fag a?e subt?acted f? om the ?ccumu?ato? . the ?esu?t is sto?ed in the ?ccumu?ato? . note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. ?cc ?cc D [m] D c ov ? z? ?c? c subt?act data memo?y f?om ?cc with ca??y and ?esu?t in data memo?y the contents of the specifed data memory and the complement of the carry fag a?e subt? acted f? om the ?ccumu?ato? . the ?esu?t is sto? ed in the data memo? y. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. ?cc ?cc D [m] D c ov ? z? ?c? c ski? if dec?ement data memo?y is 0 the contents of the specifed data memory are frst decremented by 1. if the result is 0 the fo?? owing inst? uction is ski??ed. ?s this ?equi? es the inse? tion of a dummy inst?uction whi?e the next inst?uction is fetched? it is a two cyc?e inst? uction. if the ?esu?t is not 0 the ??og?am ??oceeds with the fo??owing inst?uction. [m] [m] D 1 ski? if [m]=0 none ski? if dec?ement data memo?y is ze?o with ?esu?t in ?cc the contents of the specifed data memory are frst decremented by 1. if the result is 0? the fo?? owing inst? uction is ski?? ed. the ?esu? t is sto? ed in the ?ccumu?ato? but the specifed data memory contents remain unchanged. as this requires the inse? tion of a dummy inst?uction whi? e the next inst? uction is fetched? it is a two cyc? e inst? uction. if the ? esu? t is not 0 ? the ??og? am ?? oceeds with the fo ?? owing inst?uction. ?cc [m] D 1 ski? if ?cc=0 none rrca [m] desc?i?tion o?e?ation affected fag(s) sbc a,[m] desc?i?tion o?e?ation affected fag(s) sbcm a,[m] desc?i?tion o?e?ation affected fag(s) sdz [m] desc?i?tion o?e?ation affected fag(s) sdza [m] desc?i?tion o?e?ation affected fag(s)
rev. 1.00 ??6 ???i? 0?? ?01? rev. 1.00 ??7 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi set data memo?y each bit of the specifed data memory is set to 1. [m] ffh none set bit of data memo?y bit i of the specifed data memory is set to 1. [m].1 1 none ski? if inc?ement data memo?y is 0 the contents of the specifed data memory are frst incremented by 1. if the result is 0? the fo?? owing inst? uction is ski??ed. ?s this ?equi? es the inse? tion of a dummy inst?uction whi? e the next inst? uction is fetched? it is a two cyc?e inst? uction. if the ?esu?t is not 0 the ??og?am ??oceeds with the fo??owing inst?uction. [m] [m] + 1 ski? if [m]=0 none ski? if inc?ement data memo?y is ze?o with ?esu?t in ?cc the contents of the specifed data memory are frst incremented by 1. if the result is 0? the fo??owing inst?uction is ski?? ed. the ?esu?t is sto?ed in the ?ccumu?ato? but the specifed data memory contents remain unchanged. as this requires the inse? tion of a dummy inst? uction whi? e the next inst? uction is fetched? it is a two cyc?e inst? uction. if the ?esu? t is not 0 the ??og?am ?? oceeds with the fo?? owing inst?uction. ?cc [m] + 1 ski? if ?cc=0 none ski? if bit i of data memo?y is not 0 if bit i of the specifed data memory is not 0, the following instruction is skipped. ?s this ?equi?es the inse?tion of a dummy inst?uction whi?e the next inst?uction is fetched? it is a two cyc? e inst? uction. if the ?esu? t is 0 the ??og?am ?? oceeds with the fo??owing inst?uction. skip if [m].i 0 none subt?act data memo?y f?om ?cc the specifed data memory is subtracted from the contents of the accumulator. the ? esu? t is sto ? ed in the ? ccumu ? ato ? . note that if the ? esu? t of subt ? action is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. ?cc ?cc D [m] ov ? z? ?c? c set [m] desc?i?tion o?e?ation affected fag(s) set [m].i desc?i?tion o?e?ation affected fag(s) siz [m] desc?i?tion o?e?ation affected fag(s) siza [m] desc?i?tion o?e?ation affected fag(s) snz [m].i desc?i?tion o?e?ation affected fag(s) sub a,[m] desc?i?tion o?e?ation affected fag(s)
rev. 1.00 ??8 ???i? 0?? ?01? rev. 1.00 ??9 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi subt?act data memo?y f?om ?cc with ?esu?t in data memo?y the specifed data memory is subtracted from the contents of the accumulator. the ?esu?t is sto? ed in the data memo? y. note that if the ?esu?t of subt? action is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. [m] ?cc D [m] ov ? z? ?c? c subt?act immediate data f?om ?cc the immediate data specifed by the code is subtracted from the contents of the ? ccumu ? ato? . the ? esu? t is sto? ed in the ? ccumu ? ato? . note that if the ? esu? t of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. ?cc ?cc D x ov ? z? ?c? c swa? nibb?es of data memo?y the ?ow-o?de? and high-o?de? nibb? es of the s? ecified data memo? y a? e inte?changed. [m].3~[m].0?[m].7~[m].4 none swa? nibb?es of data memo?y with ?esu?t in ?cc the ?ow-o?de? and high-o?de? nibb? es of the s? ecified data memo? y a? e inte ? changed. the ?esu? t is sto?ed in the ?ccumu?ato? . the contents of the data memo?y ?emain unchanged. ?cc.?~?cc.0 [m].7~[m].4 ?cc.7~?cc.4 [m].?~[m].0 none ski? if data memo?y is 0 if the contents of the s ? ecified data memo?y is 0? the fo ??owing inst ? uction is ski??ed. ?s this ?equi?es the inse?tion of a dummy inst?uction whi? e the next inst?uction is fetched? it is a two cyc?e inst?uction. if the ?esu?t is not 0 the ??og?am ??oceeds with the fo??owing inst?uction. ski? if [m]=0 none ski? if data memo?y is 0 with data movement to ?cc the contents of the specifed data memory are copied to the accumulator. if the va? ue is ze?o? the fo?? owing inst? uction is ski??ed. ?s this ?equi? es the inse? tion of a dummy inst?uction whi? e the next inst? uction is fetched? it is a two cyc?e inst?uction. if the ?esu?t is not 0 the ??og?am ??oceeds with the fo??owing inst?uction. ?cc [m] ski? if [m]=0 none subm a,[m] desc?i?tion o?e?ation affected fag(s) sub a,x desc?i?tion o?e?ation affected fag(s) swap [m] desc?i?tion o?e?ation affected fag(s) swapa [m] desc?i?tion o?e?ation affected fag(s) sz [m] desc?i?tion o?e?ation affected fag(s) sza [m] desc?i?tion o?e?ation affected fag(s)
rev. 1.00 ??8 ???i? 0?? ?01? rev. 1.00 ??9 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi ski? if bit i of data memo?y is 0 if bit i of the specifed data memory is 0, the following instruction is skipped. as this ?equi? es the inse? tion of a dummy inst ? uction whi? e the next inst ? uction is fetched? it is a two cyc?e inst?uction. if the ?esu?t is not 0? the ??og?am ?? oceeds with the fo??owing inst?uction. ski? if [m].i=0 none read tab? e to tblh and data memo?y the ? ow byte of the ??og? am code add? essed by the tab?e ?ointe? (tblp/tbhp) is moved to the specifed data memory and the high byte transferred to tblh. [m] ??og?am code (?ow byte) tblh ??og?am code (high byte) none read tab?e (?ast ? age) to tblh and data memo?y the ?ow byte of the ??og?am code (?ast ?age) add?essed by the tab?e ?ointe? (tblp/tbhp) is moved to the specifed data memory and the high byte moved to tblh. [m] ??og?am code (?ow byte) tblh ??og?am code (high byte) none logica? xor data memo?y to ?cc data in the accumulator and the specifed data memory perform a bitwise logical xor o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " xor " [m] z logica? xor ?cc to data memo?y data in the specifed data memory and the accumulator perform a bitwise logical xor o?e? ation. the ?esu?t is sto?ed in the data memo? y. [m] ?cc " xor " [m] z logica? xor immediate data to ?cc data in the ?ccumu?ato? and the s?ecified immediate data ?e?fo? m a bitwise ?ogica? xor o?e? ation. the ?esu?t is sto?ed in the ?ccumu?ato? . ?cc ?cc " xor " x z sz [m].i desc?i?tion o?e?ation affected fag(s) tabrd [m] desc?i?tion o?e?ation affected fag(s) tabrdl [m] desc?i?tion o?e?ation affected fag(s) xor a,[m] desc?i?tion o?e?ation affected fag(s) xorm a,[m] desc?i?tion o?e?ation affected fag(s) xor a,x desc?i?tion o?e?ation affected fag(s)
rev. 1.00 ?40 ???i? 0?? ?01? rev. 1.00 ?41 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information. additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product tape and reel specifcations) ? packing meterials information ? carton information ? pb free products ? green packages products
rev. 1.00 ?40 ???i? 0?? ?01? rev. 1.00 ?41 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi 28-pin ssop(150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 ? 0.244 b 0.150 ? 0.157 c 0.008 ? 0.012 c? 0.386 ? 0.394 d 0.054 ? 0.060 e ? 0.025 ? f 0.004 ? 0.010 g 0.022 ? 0.028 h 0.007 ? 0.010 0 ? 8 symbol dimensions in mm min. nom. max. a 5.79 ? 6.20 b 3.81 ? 3.99 c 0.20 ? 0.30 c? 9.80 ? 10.01 d 1.37 ? 1.52 e ? 0.64 ? f 0.10 ? 0.25 g 0.56 ? 0.71 h 0.18 ? 0.25 0 ? 8
rev. 1.00 ?4? ???i? 0?? ?01? rev. 1.00 ?4? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi saw type 40-pin (6mm6mm for 0.75mm) qfn outline dimensions gtk symbol dimensions in inch min. nom. max. ? 0.0?8 0.0?0 0.0?1 ?1 0.000 0.001 0.00? ?? D 0.008 D b 0.007 0.010 0.01? d D 0.??6 D e D 0.??6 D e D 0.0?0 D d? 0.17? 0.177 0.179 e? 0.17? 0.177 0.179 l 0.014 0.016 0.018 k 0.008 D D symbol dimensions in mm min. nom. max. ? 0.70 0.75 0.80 ?1 0.00 0.0? 0.05 ?? D 0.?0 D b 0.18 0.?5 0.?0 d D 6.00 D e D 6.00 D e D 0.50 D d? 4.40 4.50 4.55 e? 4.40 4.50 4.55 l 0.?5 0.40 0.45 k 0.?0 D D
rev. 1.00 ?4? ???i? 0?? ?01? rev. 1.00 ?4? ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi 48-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. ? 0.?50 D 0.?58 b 0.?7? D 0.?80 c 0.?50 D 0.?58 d 0.?7? D 0.?80 e D 0.0?0 D f D 0.008 D g 0.05? D 0.057 h D D 0.06? i D 0.004 D j 0.018 D 0.0?0 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. ? 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.50 D f D 0.?0 D g 1.?5 D 1.45 h D D 1.60 i D 0.10 D j 0.45 D 0.75 k 0.10 D 0.?0 0 D 7
rev. 1.00 ?44 ???i? 0?? ?01? rev. 1.00 ?45 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi 64-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. ? 0.?50 D 0.?58 b 0.?7? D 0.?80 c 0.?50 D 0.?58 d 0.?7? D 0.?80 e D 0.016 D f 0.005 D 0.009 g 0.05? D 0.057 h D D 0.06? i 0.00? D 0.006 j 0.018 D 0.0?0 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. ? 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.40 D f 0.1? D 0.?? g 1.?5 D 1.45 h D D 1.60 i 0.05 D 0.15 j 0.45 D 0.75 k 0.09 D 0.?0 0 D 7
rev. 1.00 ?44 ???i? 0?? ?01? rev. 1.00 ?45 ???i? 0?? ?01? HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi HT66FB540/ht66fb550/ht66fb560 a/d flash usb 8-bit mcu with spi co?y?ight ? ?01? by holtek semiconductor inc. the info?mation a??ea?ing in this data sheet is be?ieved to be accu? ate at the time of ?ub?ication. howeve ?? ho?tek assumes no ?es?onsibi?ity a?ising f?om the use of the specifcations described. the applications mentioned herein are used solely fo? the ?u?? ose of i??ust? ation and ho? tek makes no wa?? anty o? ?e?? esentation that such a ??? ications wi?? be suitab? e without fu? the ? modification ? no? ? ecommends the use of its ??oducts fo? a???ication that may ??esent a ?isk to human ?ife due to ma?function o? othe?wise. ho?tek's ??oducts a?e not autho?ized fo? use as c?itica? com? onents in ? ife su??o? t devices o? systems. ho?tek ?ese? ves the ? ight to a?te? its products without prior notifcation. for the most up-to-date information, please visit ou? web site at htt? ://www.ho?tek.com .

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